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tapasco
tapasco
Commits
4286de8c
Commit
4286de8c
authored
Dec 13, 2017
by
Jens Korinth
Browse files
Implement 256 register file r/w for testing purposes
* manually tested with Xilinx AXI Verification IP, looks fine
parent
04dddcf9
Changes
1
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Inline
Side-by-side
src/main/scala/AxiModuleBuilder.scala
View file @
4286de8c
...
...
@@ -50,6 +50,10 @@ object AxiModuleBuilder extends ModuleBuilder {
))
))(
Axi4Lite
.
Configuration
(
AddrWidth
(
32
),
Axi4Lite
.
Width32
))
val
largeRegisterFile
=
new
axi4lite
.
RegisterFile
.
Configuration
(
addressWordBits
=
8
,
regs
=
(
0
until
256
map
{
i
=>
i
*
4
->
new
Register
(
Some
(
s
"ConfigReg_$i"
),
width
=
Axi4Lite
.
Width32
)
}).
toMap
)(
Axi4Lite
.
Configuration
(
AddrWidth
(
32
),
Axi4Lite
.
Width32
))
val
modules
:
Seq
[
ModuleDef
]
=
Seq
(
ModuleDef
(
// test module with fixed data
None
,
...
...
@@ -132,6 +136,21 @@ object AxiModuleBuilder extends ModuleBuilder {
case
_
=>
()
})
)
),
ModuleDef
(
// large AXI Register File
Some
(
largeRegisterFile
),
()
=>
new
RegisterFile
(
largeRegisterFile
),
CoreDefinition
.
withActions
(
name
=
"LargeRegisterFile"
,
vendor
=
"esa.cs.tu-darmstadt.de"
,
library
=
"chisel"
,
version
=
"0.2"
,
root
=
root
(
"RegisterFile"
),
postBuildActions
=
Seq
(
_
match
{
case
Some
(
cfg
:
RegisterFile.Configuration
)
=>
cfg
.
dumpAddressMap
(
root
(
"RegisterFile"
))
case
_
=>
()
})
)
)
)
}
Jens Korinth
@jk
mentioned in commit
17f0d672
·
Mar 05, 2018
mentioned in commit
17f0d672
mentioned in commit 17f0d67240ebf5d7e1d0be9162d272b04256c47d
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