Commit 4286de8c authored by Jens Korinth's avatar Jens Korinth
Browse files

Implement 256 register file r/w for testing purposes

* manually tested with Xilinx AXI Verification IP, looks fine
parent 04dddcf9
......@@ -50,6 +50,10 @@ object AxiModuleBuilder extends ModuleBuilder {
))
))(Axi4Lite.Configuration(AddrWidth(32), Axi4Lite.Width32))
val largeRegisterFile = new axi4lite.RegisterFile.Configuration(addressWordBits = 8, regs = (0 until 256 map { i =>
i * 4 -> new Register(Some(s"ConfigReg_$i"), width = Axi4Lite.Width32)
}).toMap)(Axi4Lite.Configuration(AddrWidth(32), Axi4Lite.Width32))
val modules: Seq[ModuleDef] = Seq(
ModuleDef( // test module with fixed data
None,
......@@ -132,6 +136,21 @@ object AxiModuleBuilder extends ModuleBuilder {
case _ => ()
})
)
),
ModuleDef( // large AXI Register File
Some(largeRegisterFile),
() => new RegisterFile(largeRegisterFile),
CoreDefinition.withActions(
name = "LargeRegisterFile",
vendor = "esa.cs.tu-darmstadt.de",
library = "chisel",
version = "0.2",
root = root("RegisterFile"),
postBuildActions = Seq(_ match {
case Some(cfg: RegisterFile.Configuration) => cfg.dumpAddressMap(root("RegisterFile"))
case _ => ()
})
)
)
)
}
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