Start implementation of data width conversion spec

src/test/scala/DataWidthConverterCorrectnessSpec.scala

+package chisel.miscutils
+import  chisel3.iotesters.{ChiselFlatSpec, Driver, PeekPokeTester}
+import  org.scalacheck._, org.scalacheck.Prop._
+import  org.scalatest.prop.Checkers
+import  generators._
+
+class DataWidthConverterCorrectnessSpec extends ChiselFlatSpec with Checkers {
+  behavior of "DataWidthConverter"
+
+  it should "say hello" in check({println("hello"); true})
+
+  it should "preserve data integrity in arbitrary conversions" in
+    check(forAll(bitWidthGen(64), Arbitrary.arbitrary[Boolean]) { case (inW, littleEndian) =>
+      forAll(conversionWidthGen(inW)) { outW =>
+        println("Testing bitwidth conversion from %d bits -> %d bits (%s)"
+          .format(inW:Int, outW:Int, if (littleEndian) "little-endian" else "big-endian"))
+        Driver.execute(Array("--fint-write-vcd", "--target-dir", "test/DataWidthConverter"),
+            () => new DataWidthConverterHarness(inW, outW, littleEndian, 0))
+          { m => new DataWidthConverterCorrectnessTester(m) }
+      }
+    }, minSuccessful(20))
+}

src/test/scala/DataWidthConverterSuiteCorrectness.scala

@@ -6,37 +6,6 @@ import  org.scalatest.junit.JUnitSuite
 import  scala.math._
 import  java.nio.file.Paths
 
-class SlowQueue(width: Int, val delay: Int = 10) extends Module {
-  val io = IO(new Bundle {
-    val enq = Flipped(Decoupled(UInt(width.W)))
-    val deq = Decoupled(UInt(width.W))
-    val dly = Input(UInt(log2Ceil(delay).W))
-  })
-
-  val waiting :: ready :: Nil = Enum(2)
-  val state = RegInit(init = ready)
-
-  val wr = Reg(UInt(log2Ceil(delay).W))
-
-  io.deq.bits  := io.enq.bits
-  io.enq.ready := io.deq.ready && state === ready
-  io.deq.valid := io.enq.valid && state === ready
-
-  when (reset) {
-    state := ready
-  }
-  .otherwise {
-    when (state === ready && io.enq.ready && io.deq.valid) {
-      state := waiting
-      wr    := io.dly
-    }
-    when (state === waiting) {
-      wr := wr - 1.U
-      when (wr === 0.U) { state := ready }
-    }
-  }
-}
-
 /**
  * DataWidthConverterHarness: Correctness test harness.
  * A DecoupledDataSource with random data is connected to a pair

src/test/scala/SlowQueue.scala

+package chisel.miscutils
+import  chisel3._
+import  chisel3.util._
+
+/** A slow queue which delays each element by a configurable delay. */
+class SlowQueue(width: Int, val delay: Int = 10) extends Module {
+  val io = IO(new Bundle {
+    val enq = Flipped(Decoupled(UInt(width.W)))
+    val deq = Decoupled(UInt(width.W))
+    val dly = Input(UInt(log2Ceil(delay).W))
+  })
+
+  val waiting :: ready :: Nil = Enum(2)
+  val state = RegInit(ready)
+
+  val wr = Reg(UInt(log2Ceil(delay).W))
+
+  io.deq.bits  := io.enq.bits
+  io.enq.ready := io.deq.ready && state === ready
+  io.deq.valid := io.enq.valid && state === ready
+
+  when (reset) {
+    state := ready
+  }
+  .otherwise {
+    when (state === ready && io.enq.ready && io.deq.valid) {
+      state := waiting
+      wr    := io.dly
+    }
+    when (state === waiting) {
+      wr := wr - 1.U
+      when (wr === 0.U) { state := ready }
+    }
+  }
+}
+