Commit 45274e95 authored by Carsten Heinz's avatar Carsten Heinz
Browse files

Update System Cache ip version and implement name changes

parent e54a60fc
......@@ -4,7 +4,7 @@ dict set stdcomps axi_sc vlnv "xilinx.com:ip:smartconnect:1.0"
dict set stdcomps ps vlnv "xilinx.com:ip:processing_system7:5.5"
dict set stdcomps ps_bfm vlnv "xilinx.com:ip:processing_system7_bfm:2.0"
dict set stdcomps axi_irqc vlnv "xilinx.com:ip:axi_intc:4.1"
dict set stdcomps axi_cache vlnv "xilinx.com:ip:system_cache:3.0"
dict set stdcomps axi_cache vlnv "xilinx.com:ip:system_cache:4.0"
dict set stdcomps xlconcat vlnv "xilinx.com:ip:xlconcat:2.1"
dict set stdcomps xlslice vlnv "xilinx.com:ip:xlslice:1.0"
dict set stdcomps xlconst vlnv "xilinx.com:ip:xlconstant:1.1"
......@@ -16,7 +16,7 @@ dict set stdcomps bluedma_x16 vlnv "esa.informatik.tu-darmstadt.de:
dict set stdcomps msixusptrans vlnv "esa.informatik.tu-darmstadt.de:user:MSIxUSPTranslator:1.0"
dict set stdcomps oled_ctrl vlnv "esa.cs.tu-darmstadt.de:user:oled_pc:1.0"
dict set stdcomps mm_to_lite vlnv "esa.cs.tu-darmstadt.de:user:mm_to_lite:1.0"
dict set stdcomps system_cache vlnv "xilinx.com:ip:system_cache:3.1"
dict set stdcomps system_cache vlnv "xilinx.com:ip:system_cache:4.0"
dict set stdcomps mig_core vlnv "xilinx.com:ip:mig_7series:4.0"
dict set stdcomps axi_pcie3_0 vlnv "xilinx.com:ip:axi_pcie3:3.0"
dict set stdcomps tapasco_status vlnv "esa.cs.tu-darmstadt.de:tapasco:tapasco_status:1.4"
......@@ -35,4 +35,4 @@ dict set stdcomps 10g_mac vlnv "xilinx.com:ip:axi_10g_ethernet:
dict set stdcomps axi_iic vlnv "xilinx.com:ip:axi_iic:2.0"
dict set stdcomps util_buf vlnv "xilinx.com:ip:util_ds_buf:2.1"
dict set stdcomps pciebridgetolite vlnv "esa.informatik.tu-darmstadt.de:user:PCIeBridgeToLite:1.0"
dict set stdcomps pciebridgetolite_x16 vlnv "esa.informatik.tu-darmstadt.de:user:PCIeBridgeToLite_x16:1.0"
\ No newline at end of file
dict set stdcomps pciebridgetolite_x16 vlnv "esa.informatik.tu-darmstadt.de:user:PCIeBridgeToLite_x16:1.0"
......@@ -322,10 +322,10 @@ namespace eval ::tapasco::ip {
set inst [create_bd_cell -type ip -vlnv [dict get $stdcomps system_cache vlnv] $name]
set_property -dict [list \
CONFIG.C_CACHE_SIZE $size \
CONFIG.C_M_AXI_THREAD_ID_WIDTH {6} \
CONFIG.C_M0_AXI_THREAD_ID_WIDTH {6} \
CONFIG.C_NUM_GENERIC_PORTS $num_ports \
CONFIG.C_NUM_OPTIMIZED_PORTS {0} \
CONFIG.C_NUM_SETS $num_sets \
CONFIG.C_NUM_WAYS $num_sets \
] $inst
return $inst
}
......
......@@ -203,11 +203,13 @@
set cache [tapasco::ip::create_axi_cache "cache_l2" 1 \
[dict get [tapasco::get_feature "Cache"] "size"] \
[dict get [tapasco::get_feature "Cache"] "associativity"]]
# set slave port width to 512bit, otherwise uses (not working) width conversion in SmartConnect
set_property CONFIG.C_S0_AXI_GEN_DATA_WIDTH {512} $cache
# connect mig_ic master to cache_l2
connect_bd_intf_net [get_bd_intf_pins mig_ic/M00_AXI] [get_bd_intf_pins $cache/S0_AXI_GEN]
# connect cache_l2 to MIG
connect_bd_intf_net [get_bd_intf_pins $cache/M_AXI] [get_bd_intf_pins -regexp mig/(C0_DDR4_)?S_AXI]
connect_bd_intf_net [get_bd_intf_pins $cache/M0_AXI] [get_bd_intf_pins -regexp mig/(C0_DDR4_)?S_AXI]
} {
puts "Platform configured w/o L2 Cache"
# no cache - connect directly to MIG
......
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