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tapasco
tapasco
Commits
47d5f9d7
Commit
47d5f9d7
authored
Dec 28, 2017
by
Jens Korinth
Browse files
Fixes
#131
- Wrong name for bitstream file
parent
d2d5bf12
Pipeline
#61
passed with stage
in 3 minutes and 4 seconds
Changes
2
Pipelines
1
Hide whitespace changes
Inline
Side-by-side
src/main/scala/tapasco/activity/composers/VivadoComposer.scala
View file @
47d5f9d7
...
...
@@ -215,7 +215,7 @@ object VivadoComposer {
lazy
val
outdir
:
Path
=
cfg
.
outputDir
(
c
,
t
,
f
,
fs
)
lazy
val
logFile
:
Path
=
outdir
.
resolve
(
"%s.log"
.
format
(
c
.
id
))
lazy
val
tclFile
:
Path
=
outdir
.
resolve
(
"%s.tcl"
.
format
(
t
.
pd
.
name
))
lazy
val
bitFile
:
Path
=
outdir
.
resolve
(
"%s.bit"
.
format
(
c
.
id
))
lazy
val
bitFile
:
Path
=
logFile
.
resolve
Sibling
(
"%s.bit"
.
format
(
Composer
.
mkProjectName
(
c
,
t
,
f
)
))
lazy
val
runName
:
String
=
"%s with %s[F=%1.3f]"
.
format
(
logformat
(
c
),
t
,
f
)
lazy
val
pwrFile
:
Path
=
logFile
.
resolveSibling
(
"power.txt"
)
lazy
val
timFile
:
Path
=
logFile
.
resolveSibling
(
"timing.txt"
)
...
...
src/main/scala/tapasco/task/ComposeTask.scala
View file @
47d5f9d7
...
...
@@ -62,7 +62,7 @@ class ComposeTask(composition: Composition,
designFrequency
,
target
,
_composerResult
map
(
_
.
result
)
getOrElse
""
,
_composerResult
m
ap
(
_
.
bit
)
getOrElse
""
,
_composerResult
flatM
ap
(
_
.
bit
)
getOrElse
""
,
_composerResult
flatMap
(
_
.
log
map
(
_
.
file
))
getOrElse
""
,
_composerResult
flatMap
(
_
.
util
map
(
_
.
file
))
getOrElse
""
,
_composerResult
flatMap
(
_
.
timing
map
(
_
.
file
))
getOrElse
""
,
...
...
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