Commit 485abb90 authored by Jens Korinth's avatar Jens Korinth
Browse files

Implement support for Vivado 2017.2

parent 24d7745d
# create a dictionary of compatible VLNVs
dict set stdcomps axi_ic vlnv "xilinx.com:ip:axi_interconnect:2.1"
dict set stdcomps ps vlnv "xilinx.com:ip:processing_system7:5.5"
dict set stdcomps ps_bfm vlnv "xilinx.com:ip:processing_system7_bfm:2.0"
dict set stdcomps axi_irqc vlnv "xilinx.com:ip:axi_intc:4.1"
dict set stdcomps axi_cache vlnv "xilinx.com:ip:system_cache:3.0"
dict set stdcomps xlconcat vlnv "xilinx.com:ip:xlconcat:2.1"
dict set stdcomps xlslice vlnv "xilinx.com:ip:xlslice:1.0"
dict set stdcomps xlconst vlnv "xilinx.com:ip:xlconstant:1.1"
dict set stdcomps rst_gen vlnv "xilinx.com:ip:proc_sys_reset:5.0"
dict set stdcomps proto_conv vlnv "xilinx.com:ip:axi_protocol_converter:2.1"
dict set stdcomps bincnt vlnv "xilinx.com:ip:c_counter_binary:12.0"
dict set stdcomps dualdma vlnv "esa.informatik.tu-darmstadt.de:user:dual_dma:1.9"
dict set stdcomps oled_ctrl vlnv "esa.cs.tu-darmstadt.de:user:oled_pc:1.0"
dict set stdcomps mm_to_lite vlnv "esa.cs.tu-darmstadt.de:user:mm_to_lite:1.0"
dict set stdcomps system_cache vlnv "xilinx.com:ip:system_cache:3.1"
dict set stdcomps mig_core vlnv "xilinx.com:ip:mig_7series:4.0"
dict set stdcomps axi_pcie3_0 vlnv "xilinx.com:ip:axi_pcie3:3.0"
dict set stdcomps tapasco_status vlnv "esa.cs.tu-darmstadt.de:user:tapasco_status:1.1"
dict set stdcomps clk_wiz "xilinx.com:ip:clk_wiz:5.4"
dict set stdcomps msix_intr_ctrl vlnv "esa.informatik.tu-darmstadt.de:user:MSIXIntrCtrl:1.0"
dict set stdcomps axi_reg_slice vlnv "xilinx.com:ip:axi_register_slice:2.1"
dict set stdcomps dwidth_conv vlnv "xilinx.com:ip:axi_dwidth_converter:2.1"
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OPTION psf_version = 2.1;
BEGIN DRIVER dual_dma
OPTION supported_peripherals = (dual_dma);
OPTION copyfiles = all;
OPTION VERSION = 1.0;
OPTION NAME = dual_dma;
END DRIVER
#
# Copyright (C) 2014 David de la Chevallerie, TU Darmstadt
#
# This file is part of Tapasco (TPC).
#
# Tapasco is free software: you can redistribute it and/or modify
# it under the terms of the GNU Lesser General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# Tapasco is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU Lesser General Public License for more details.
#
# You should have received a copy of the GNU Lesser General Public License
# along with Tapasco. If not, see <http://www.gnu.org/licenses/>.
#
proc generate {drv_handle} {
xdefine_include_file $drv_handle "xparameters.h" "dual_dma" "NUM_INSTANCES" "DEVICE_ID" "C_S_AXI_BASEADDR" "C_S_AXI_HIGHADDR"
}
COMPILER=
ARCHIVER=
CP=cp
COMPILER_FLAGS=
EXTRA_COMPILER_FLAGS=
LIB=libxil.a
RELEASEDIR=../../../lib
INCLUDEDIR=../../../include
INCLUDES=-I./. -I${INCLUDEDIR}
INCLUDEFILES=*.h
LIBSOURCES=*.c
OUTS = *.o
libs:
echo "Compiling dual_dma..."
$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
make clean
include:
${CP} $(INCLUDEFILES) $(INCLUDEDIR)
clean:
rm -rf ${OUTS}
//
// Copyright (C) 2014 David de la Chevallerie, TU Darmstadt
//
// This file is part of Tapasco (TPC).
//
// Tapasco is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// Tapasco is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with Tapasco. If not, see <http://www.gnu.org/licenses/>.
//
/***************************** Include Files *******************************/
#include "dual_dma.h"
/************************** Function Definitions ***************************/
//
// Copyright (C) 2014 David de la Chevallerie, TU Darmstadt
//
// This file is part of Tapasco (TPC).
//
// Tapasco is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// Tapasco is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with Tapasco. If not, see <http://www.gnu.org/licenses/>.
//
#ifndef DUAL_DMA_H
#define DUAL_DMA_H
/****************** Include Files ********************/
#include "xil_types.h"
#include "xstatus.h"
#define DUAL_DMA_S_AXI_SLV_REG0_OFFSET 0
#define DUAL_DMA_S_AXI_SLV_REG1_OFFSET 4
#define DUAL_DMA_S_AXI_SLV_REG2_OFFSET 8
#define DUAL_DMA_S_AXI_SLV_REG3_OFFSET 12
#define DUAL_DMA_S_AXI_SLV_REG4_OFFSET 16
#define DUAL_DMA_S_AXI_SLV_REG5_OFFSET 20
#define DUAL_DMA_S_AXI_SLV_REG6_OFFSET 24
#define DUAL_DMA_S_AXI_SLV_REG7_OFFSET 28
#define DUAL_DMA_S_AXI_SLV_REG8_OFFSET 32
#define DUAL_DMA_S_AXI_SLV_REG9_OFFSET 36
#define DUAL_DMA_S_AXI_SLV_REG10_OFFSET 40
#define DUAL_DMA_S_AXI_SLV_REG11_OFFSET 44
#define DUAL_DMA_S_AXI_SLV_REG12_OFFSET 48
#define DUAL_DMA_S_AXI_SLV_REG13_OFFSET 52
#define DUAL_DMA_S_AXI_SLV_REG14_OFFSET 56
#define DUAL_DMA_S_AXI_SLV_REG15_OFFSET 60
#define DUAL_DMA_S_AXI_SLV_REG16_OFFSET 64
#define DUAL_DMA_S_AXI_SLV_REG17_OFFSET 68
#define DUAL_DMA_S_AXI_SLV_REG18_OFFSET 72
#define DUAL_DMA_S_AXI_SLV_REG19_OFFSET 76
#define DUAL_DMA_S_AXI_SLV_REG20_OFFSET 80
#define DUAL_DMA_S_AXI_SLV_REG21_OFFSET 84
#define DUAL_DMA_S_AXI_SLV_REG22_OFFSET 88
#define DUAL_DMA_S_AXI_SLV_REG23_OFFSET 92
#define DUAL_DMA_S_AXI_SLV_REG24_OFFSET 96
#define DUAL_DMA_S_AXI_SLV_REG25_OFFSET 100
#define DUAL_DMA_S_AXI_SLV_REG26_OFFSET 104
#define DUAL_DMA_S_AXI_SLV_REG27_OFFSET 108
#define DUAL_DMA_S_AXI_SLV_REG28_OFFSET 112
#define DUAL_DMA_S_AXI_SLV_REG29_OFFSET 116
#define DUAL_DMA_S_AXI_SLV_REG30_OFFSET 120
#define DUAL_DMA_S_AXI_SLV_REG31_OFFSET 124
/**************************** Type Definitions *****************************/
/**
*
* Write a value to a DUAL_DMA register. A 32 bit write is performed.
* If the component is implemented in a smaller width, only the least
* significant data is written.
*
* @param BaseAddress is the base address of the DUAL_DMAdevice.
* @param RegOffset is the register offset from the base to write to.
* @param Data is the data written to the register.
*
* @return None.
*
* @note
* C-style signature:
* void DUAL_DMA_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data)
*
*/
#define DUAL_DMA_mWriteReg(BaseAddress, RegOffset, Data) \
Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
/**
*
* Read a value from a DUAL_DMA register. A 32 bit read is performed.
* If the component is implemented in a smaller width, only the least
* significant data is read from the register. The most significant data
* will be read as 0.
*
* @param BaseAddress is the base address of the DUAL_DMA device.
* @param RegOffset is the register offset from the base to write to.
*
* @return Data is the data from the register.
*
* @note
* C-style signature:
* u32 DUAL_DMA_mReadReg(u32 BaseAddress, unsigned RegOffset)
*
*/
#define DUAL_DMA_mReadReg(BaseAddress, RegOffset) \
Xil_In32((BaseAddress) + (RegOffset))
/************************** Function Prototypes ****************************/
/**
*
* Run a self-test on the driver/device. Note this may be a destructive test if
* resets of the device are performed.
*
* If the hardware system is not built correctly, this function may never
* return to the caller.
*
* @param baseaddr_p is the base address of the DUAL_DMA instance to be worked on.
*
* @return
*
* - XST_SUCCESS if all self-test code passed
* - XST_FAILURE if any self-test code failed
*
* @note Caching must be turned off for this function to work.
* @note Self test may fail if data memory and device are not on the same bus.
*
*/
XStatus DUAL_DMA_Reg_SelfTest(void * baseaddr_p);
#endif // DUAL_DMA_H
//
// Copyright (C) 2014 David de la Chevallerie, TU Darmstadt
//
// This file is part of Tapasco (TPC).
//
// Tapasco is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// Tapasco is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with Tapasco. If not, see <http://www.gnu.org/licenses/>.
//
/***************************** Include Files *******************************/
#include "dual_dma.h"
#include "xparameters.h"
#include "stdio.h"
#include "xil_io.h"
/************************** Constant Definitions ***************************/
#define READ_WRITE_MUL_FACTOR 0x10
/************************** Function Definitions ***************************/
/**
*
* Run a self-test on the driver/device. Note this may be a destructive test if
* resets of the device are performed.
*
* If the hardware system is not built correctly, this function may never
* return to the caller.
*
* @param baseaddr_p is the base address of the DUAL_DMAinstance to be worked on.
*
* @return
*
* - XST_SUCCESS if all self-test code passed
* - XST_FAILURE if any self-test code failed
*
* @note Caching must be turned off for this function to work.
* @note Self test may fail if data memory and device are not on the same bus.
*
*/
XStatus DUAL_DMA_Reg_SelfTest(void * baseaddr_p)
{
u32 baseaddr;
int write_loop_index;
int read_loop_index;
int Index;
baseaddr = (u32) baseaddr_p;
xil_printf("******************************\n\r");
xil_printf("* User Peripheral Self Test\n\r");
xil_printf("******************************\n\n\r");
/*
* Write to user logic slave module register(s) and read back
*/
xil_printf("User logic slave module test...\n\r");
for (write_loop_index = 0 ; write_loop_index < 4; write_loop_index++)
DUAL_DMA_mWriteReg (baseaddr, write_loop_index*4, (write_loop_index+1)*READ_WRITE_MUL_FACTOR);
for (read_loop_index = 0 ; read_loop_index < 4; read_loop_index++)
if ( DUAL_DMA_mReadReg (baseaddr, read_loop_index*4) != (read_loop_index+1)*READ_WRITE_MUL_FACTOR){
xil_printf ("Error reading register value at address %x\n", (int)baseaddr + read_loop_index*4);
return XST_FAILURE;
}
xil_printf(" - slave register write/read passed\n\n\r");
return XST_SUCCESS;
}
#
# Copyright (C) 2014 David de la Chevallerie, TU Darmstadt
#
# This file is part of Tapasco (TPC).
#
# Tapasco is free software: you can redistribute it and/or modify
# it under the terms of the GNU Lesser General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# Tapasco is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU Lesser General Public License for more details.
#
# You should have received a copy of the GNU Lesser General Public License
# along with Tapasco. If not, see <http://www.gnu.org/licenses/>.
#
#has to be scoped to the dual_dma instance
set s_clk [get_clocks -of_objects [get_ports m32_axi_aclk]]
set m_clk [get_clocks -of_objects [get_ports m64_axi_aclk]]
set_false_path -through [get_ports -filter {NAME =~ *_axi_aresetn}] -to [filter [get_cells -hierarchical -filter {NAME =~ */rstblk/*}] {IS_SEQUENTIAL}]
set_max_delay -from [filter [all_fanout -from [get_ports m32_axi_aclk] -flat -endpoints_only] {IS_LEAF}] -to [filter [all_fanout -from [get_ports m64_axi_aclk] -flat -only_cells] {IS_SEQUENTIAL && (NAME !~ *dout_i_reg[*])}] -datapath_only [get_property -min PERIOD $s_clk]
set_max_delay -from [filter [all_fanout -from [get_ports m64_axi_aclk] -flat -endpoints_only] {IS_LEAF}] -to [filter [all_fanout -from [get_ports m32_axi_aclk] -flat -only_cells] {IS_SEQUENTIAL && (NAME !~ *dout_i_reg[*])}] -datapath_only [get_property -min PERIOD $m_clk]
set_disable_timing -from CLK -to O [filter [all_fanout -from [get_ports m32_axi_aclk] -flat -endpoints_only -only_cells] {PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==LUTRAM}]
set_disable_timing -from CLK -to O [filter [all_fanout -from [get_ports m64_axi_aclk] -flat -endpoints_only -only_cells] {PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==LUTRAM}]
set g_clk [get_clocks -of_objects [get_ports s_axi_aclk]]
set_max_delay -from [filter [all_fanout -from [get_ports m32_axi_aclk] -flat -endpoints_only] {IS_LEAF}] -to [filter [all_fanout -from [get_ports s_axi_aclk] -flat -only_cells] {IS_SEQUENTIAL && (NAME !~ *dout_i_reg[*])}] -datapath_only [get_property -min PERIOD $s_clk]
set_max_delay -from [filter [all_fanout -from [get_ports s_axi_aclk] -flat -endpoints_only] {IS_LEAF}] -to [filter [all_fanout -from [get_ports m32_axi_aclk] -flat -only_cells] {IS_SEQUENTIAL && (NAME !~ *dout_i_reg[*])}] -datapath_only [get_property -min PERIOD $g_clk]
set_disable_timing -from CLK -to O [filter [all_fanout -from [get_ports s_axi_aclk] -flat -endpoints_only -only_cells] {PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==LUTRAM}]
#
# Copyright (C) 2014 David de la Chevallerie, TU Darmstadt
#
# This file is part of Tapasco (TPC).
#
# Tapasco is free software: you can redistribute it and/or modify
# it under the terms of the GNU Lesser General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# Tapasco is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU Lesser General Public License for more details.
#
# You should have received a copy of the GNU Lesser General Public License
# along with Tapasco. If not, see <http://www.gnu.org/licenses/>.
#
proc create_ipi_design { offsetfile design_name } {
create_bd_design $design_name
open_bd_design $design_name
# Create Clock and Reset Ports
set ACLK_LITE [ create_bd_port -dir I -type clk ACLK_LITE ]
set_property -dict [ list CONFIG.FREQ_HZ {100000000} CONFIG.PHASE {0.000} CONFIG.CLK_DOMAIN "${design_name}_ACLK_LITE" ] $ACLK_LITE
set ARESETN_LITE [ create_bd_port -dir I -type rst ARESETN_LITE ]
set_property -dict [ list CONFIG.POLARITY {ACTIVE_LOW} ] $ARESETN_LITE
set_property CONFIG.ASSOCIATED_RESET ARESETN_LITE $ACLK_LITE
set ACLK_M64 [ create_bd_port -dir I -type clk ACLK_M64 ]
set_property -dict [ list CONFIG.FREQ_HZ {100000000} CONFIG.PHASE {0.000} CONFIG.CLK_DOMAIN "${design_name}_ACLK_M64" ] $ACLK_M64
set ARESETN_M64 [ create_bd_port -dir I -type rst ARESETN_M64 ]
set_property -dict [ list CONFIG.POLARITY {ACTIVE_LOW} ] $ARESETN_M64
set_property CONFIG.ASSOCIATED_RESET ARESETN_M64 $ACLK_M64
set ACLK_M32 [ create_bd_port -dir I -type clk ACLK_M32 ]
set_property -dict [ list CONFIG.FREQ_HZ {100000000} CONFIG.PHASE {0.000} CONFIG.CLK_DOMAIN "${design_name}_ACLK_M32" ] $ACLK_M32
set ARESETN_M32 [ create_bd_port -dir I -type rst ARESETN_M32 ]
set_property -dict [ list CONFIG.POLARITY {ACTIVE_LOW} ] $ARESETN_M32
set_property CONFIG.ASSOCIATED_RESET ARESETN_M32 $ACLK_M32
# Create instance: dual_dma_0, and set properties
set dual_dma_0 [ create_bd_cell -type ip -vlnv esa.informatik.tu-darmstadt.de:user:dual_dma:1.0 dual_dma_0]
# Create External ports
set IRQ [ create_bd_port -dir O IRQ ]
connect_bd_net -net IRQ_net [get_bd_ports IRQ] [get_bd_pins dual_dma_0/IRQ]
# Create axi interconnect
set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0]
set_property -dict [list CONFIG.NUM_SI {2} CONFIG.NUM_MI {1} CONFIG.STRATEGY {2} CONFIG.S00_HAS_DATA_FIFO {2} CONFIG.S01_HAS_DATA_FIFO {2}] [get_bd_cells axi_interconnect_0] $axi_interconnect_0
# Create port connections
connect_bd_net -net aclk_net_m64 [get_bd_ports ACLK_M64] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins axi_interconnect_0/S01_ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK]
connect_bd_net -net aresetn_net_m64 [get_bd_ports ARESETN_M64] [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins axi_interconnect_0/S01_ARESETN] [get_bd_pins axi_interconnect_0/M00_ARESETN]
# Create instance: master_0, and set properties
set master_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:cdn_axi_bfm master_0]
set_property -dict [ list CONFIG.C_PROTOCOL_SELECTION {2} ] $master_0
# Create interface connections
connect_bd_intf_net [get_bd_intf_pins master_0/M_AXI_LITE] [get_bd_intf_pins dual_dma_0/S_AXI]
# Create port connections
connect_bd_net -net aclk_net_lite [get_bd_ports ACLK_LITE] [get_bd_pins master_0/M_AXI_LITE_ACLK] [get_bd_pins dual_dma_0/S_AXI_ACLK]
connect_bd_net -net aresetn_net_lite [get_bd_ports ARESETN_LITE] [get_bd_pins master_0/M_AXI_LITE_ARESETN] [get_bd_pins dual_dma_0/S_AXI_ARESETN]
# Create instance: master_1, and set properties
set master_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:cdn_axi_bfm master_1]
set_property -dict [ list CONFIG.C_PROTOCOL_SELECTION {2} CONFIG.C_M_AXI4_LITE_ADDR_WIDTH {64} ] $master_1
# Create interface connections
connect_bd_intf_net [get_bd_intf_pins master_1/M_AXI_LITE] [get_bd_intf_pins axi_interconnect_0/S00_AXI]
# Create port connections
connect_bd_net -net [get_bd_nets aclk_net_m64] [get_bd_ports ACLK_M64] [get_bd_pins master_1/m_axi_lite_aclk]
connect_bd_net -net [get_bd_nets aresetn_net_m64] [get_bd_ports ARESETN_M64] [get_bd_pins master_1/m_axi_lite_aresetn]
# Create instance: slave_0, and set properties
set slave_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:cdn_axi_bfm slave_0]
set_property -dict [ list CONFIG.C_PROTOCOL_SELECTION {1} CONFIG.C_MODE_SELECT {1} CONFIG.C_S_AXI4_ADDR_WIDTH {64} CONFIG.C_S_AXI4_HIGHADDR {0x500000006000FFFF} CONFIG.C_S_AXI4_BASEADDR {0x5000000060000000} CONFIG.C_S_AXI4_MEMORY_MODEL_MODE {1} ] $slave_0
# Create interface connections
connect_bd_intf_net [get_bd_intf_pins slave_0/S_AXI] [get_bd_intf_pins axi_interconnect_0/M00_AXI]
connect_bd_intf_net [get_bd_intf_pins dual_dma_0/M64_AXI] [get_bd_intf_pins axi_interconnect_0/S01_AXI]
# Create port connections
connect_bd_net -net [get_bd_nets aclk_net_m64] [get_bd_ports ACLK_M64] [get_bd_pins slave_0/S_AXI_ACLK] [get_bd_pins dual_dma_0/M64_AXI_ACLK]
connect_bd_net -net [get_bd_nets aresetn_net_m64] [get_bd_ports ARESETN_M64] [get_bd_pins slave_0/S_AXI_ARESETN] [get_bd_pins dual_dma_0/M64_AXI_ARESETN]
# Create instance: slave_1, and set properties
set slave_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:cdn_axi_bfm slave_1]
set_property -dict [ list CONFIG.C_PROTOCOL_SELECTION {1} CONFIG.C_MODE_SELECT {1} CONFIG.C_S_AXI4_HIGHADDR {0x4000FFFF} CONFIG.C_S_AXI4_BASEADDR {0x40000000} CONFIG.C_S_AXI4_MEMORY_MODEL_MODE {1} ] $slave_1
# Create interface connections
connect_bd_intf_net [get_bd_intf_pins slave_1/S_AXI] [get_bd_intf_pins dual_dma_0/M32_AXI]
# Create port connections
connect_bd_net -net aclk_net_m32 [get_bd_ports ACLK_M32] [get_bd_pins slave_1/S_AXI_ACLK] [get_bd_pins dual_dma_0/M32_AXI_ACLK]
connect_bd_net -net aresetn_net [get_bd_ports ARESETN_M32] [get_bd_pins slave_1/S_AXI_ARESETN] [get_bd_pins dual_dma_0/M32_AXI_ARESETN]
# Create instance: slave_2, and set properties
#set slave_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:cdn_axi_bfm slave_2]
#set_property -dict [ list CONFIG.C_PROTOCOL_SELECTION {3} CONFIG.C_MODE_SELECT {1} CONFIG.C_S_AXIS_TDATA_WIDTH {32} CONFIG.C_S_AXIS_STROBE_NOT_USED {1} CONFIG.C_S_AXIS_KEEP_NOT_USED {1} ] $slave_2
# Create interface connections
#connect_bd_intf_net -intf_net slave_2_s_axis [get_bd_intf_pins dual_dma_0/M_AXIS] [get_bd_intf_pins slave_2/S_AXIS]
# Create port connections
#connect_bd_net -net aclk_net [get_bd_ports ACLK] [get_bd_pins dual_dma_0/M_AXIS_ACLK] [get_bd_pins slave_2/S_AXIS_ACLK]
#connect_bd_net -net aresetn_net [get_bd_ports ARESETN] [get_bd_pins dual_dma_0/M_AXIS_ARESETN] [get_bd_pins slave_2/S_AXIS_ARESETN]
# Auto assign address
assign_bd_address
# Copy all address to interface_address.vh file
set bd_path [file dirname [get_property NAME [get_files ${design_name}.bd]]]
upvar 1 $offsetfile offset_file
set offset_file "${bd_path}/dual_dma_v1_0_tb_include.vh"
set fp [open $offset_file "w"]
puts $fp "`ifndef dual_dma_v1_0_tb_include_vh_"
puts $fp "`define dual_dma_v1_0_tb_include_vh_\n"
puts $fp "//Configuration current bd names"
puts $fp "`define BD_INST_NAME ${design_name}_i"
puts $fp "`define BD_WRAPPER ${design_name}_wrapper\n"
puts $fp "//Configuration address parameters"
set offset [get_property OFFSET [get_bd_addr_segs -of_objects [get_bd_addr_spaces master_0/Data_lite]]]
set offset_hex [string replace $offset 0 1 "32'h"]
puts $fp "`define S_AXI_SLAVE_ADDRESS ${offset_hex}"
puts $fp "`endif"
close $fp
}
set ip_path [file dirname [file normalize [get_property XML_FILE_NAME [ipx::get_cores esa.informatik.tu-darmstadt.de:user:dual_dma:1.0]]]]
set test_bench_file ${ip_path}/example_designs/bfm_design/dual_dma_v1_0_tb.v
set interface_address_vh_file ""
# Set IP Repository and Update IP Catalogue
set repo_paths [get_property ip_repo_paths [current_fileset]]
if { [lsearch -exact -nocase $repo_paths $ip_path ] == -1 } {
set_property ip_repo_paths "$ip_path [get_property ip_repo_paths [current_fileset]]" [current_fileset]
update_ip_catalog
}
set design_name ""
set all_bd {}
set all_bd_files [get_files *.bd -quiet]
foreach file $all_bd_files {
set file_name [string range $file [expr {[string last "/" $file] + 1}] end]
set bd_name [string range $file_name 0 [expr {[string last "." $file_name] -1}]]
lappend all_bd $bd_name
}
for { set i 1 } { 1 } { incr i } {
set design_name "dual_dma_v1_0_bfm_${i}"
if { [lsearch -exact -nocase $all_bd $design_name ] == -1 } {
break
}
}
create_ipi_design interface_address_vh_file ${design_name}
validate_bd_design
set wrapper_file [make_wrapper -files [get_files ${design_name}.bd] -top -force]
import_files -force -norecurse $wrapper_file
set_property SOURCE_SET sources_1 [get_filesets sim_1]
import_files -fileset sim_1 -norecurse -force $test_bench_file
remove_files -quiet -fileset sim_1 dual_dma_v1_0_tb_include.vh
import_files -fileset sim_1 -norecurse -force $interface_address_vh_file
set_property top dual_dma_v1_0_tb [get_filesets sim_1]
set_property top_lib {} [get_filesets sim_1]
set_property top_file {} [get_filesets sim_1]
launch_xsim -simset sim_1 -mode behavioral
restart
run 1000 us
//
// Copyright (C) 2014 David de la Chevallerie, TU Darmstadt
//
// This file is part of Tapasco (TPC).
//
// Tapasco is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// Tapasco is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with Tapasco. If not, see <http://www.gnu.org/licenses/>.
//
`timescale 1 ns / 1 ps
`include "dual_dma_v1_0_tb_include.vh"
// lite_response Type Defines
`define RESPONSE_OKAY 2'b00
`define RESPONSE_EXOKAY 2'b01
`define RESP_BUS_WIDTH 2
`define BURST_TYPE_INCR 2'b01
`define BURST_TYPE_WRAP 2'b10
// AMBA AXI4 Lite Range Constants
`define S_AXI_MAX_BURST_LENGTH 1
`define S_AXI_REGISTER 8
//`define S_AXI_DATA_BUS_WIDTH 64
`define S_AXI_DATA_BUS_WIDTH 32
`define S_AXI_ADDRESS_BUS_WIDTH 32
`define S_AXI_MAX_DATA_SIZE (`S_AXI_DATA_BUS_WIDTH*`S_AXI_MAX_BURST_LENGTH)/8
`define SLAVE_AXI_ADDRESS_BUS_WIDTH 64
`define SLAVE_AXI_BASE_ADDRESS 5000000060000000
// Streaming defines
`define MAX_BURST_LENGTH 1
`define DESTVALID_FALSE 1'b0
`define DESTVALID_TRUE 1'b1
`define IDVALID_TRUE 1'b1
`define IDVALID_FALSE 1'b0
`define DATA_BUS_WIDTH 32
`define ID_BUS_WIDTH 8
`define DEST_BUS_WIDTH 4
`define USER_BUS_WIDTH 8
`define MAX_PACKET_SIZE 10
`define MAX_OUTSTANDING_TRANSACTIONS 8
`define STROBE_NOT_USED 0
`define KEEP_NOT_USED 0
module dual_dma_v1_0_tb;
reg tb_ACLK_LITE;
reg tb_ARESETN_LITE;
reg tb_ACLK_M64;
reg tb_ARESETN_M64;
reg tb_ACLK_M32;
reg tb_ARESETN_M32;
wire tb_IRQ;
// Create an instance of the example tb
`BD_WRAPPER dut ( .ACLK_LITE(tb_ACLK_LITE),
.ARESETN_LITE(tb_ARESETN_LITE),
.ACLK_M64(tb_ACLK_M64),
.ARESETN_M64(tb_ARESETN_M64),