Finish data width converter correctness spec

src/test/scala/DataWidthConverterCorrectnessSpec.scala

@@ -7,15 +7,13 @@ import  generators._
 class DataWidthConverterCorrectnessSpec extends ChiselFlatSpec with Checkers {
   behavior of "DataWidthConverter"
 
-  it should "say hello" in check({println("hello"); true})
-
   it should "preserve data integrity in arbitrary conversions" in
     check(forAll(bitWidthGen(64), Arbitrary.arbitrary[Boolean]) { case (inW, littleEndian) =>
       forAll(conversionWidthGen(inW)) { outW =>
         println("Testing bitwidth conversion from %d bits -> %d bits (%s)"
           .format(inW:Int, outW:Int, if (littleEndian) "little-endian" else "big-endian"))
         Driver.execute(Array("--fint-write-vcd", "--target-dir", "test/DataWidthConverter"),
-            () => new DataWidthConverterHarness(inW, outW, littleEndian, 0))
+            () => new DataWidthConverterHarness(inW, outW, littleEndian))
           { m => new DataWidthConverterCorrectnessTester(m) }
       }
     }, minSuccessful(20))

src/test/scala/DataWidthConverterSuiteCorrectness.scala

@@ -16,6 +16,7 @@ import  java.nio.file.Paths
  * varying speed of consumption.
  **/
 class DataWidthConverterHarness(inWidth: Int, outWidth: Int, littleEndian: Boolean, delay: Int = 10) extends Module {
+  require (delay > 0, "delay bitwidth must be > 0")
   val io = IO(new Bundle {
     val dly = Input(UInt(log2Ceil(delay).W))
     val dsrc_out_valid = Output(Bool())

src/test/scala/generators.scala

 package chisel.miscutils
 import  org.scalacheck._
 import  SignalGenerator._
-import  scala.language.implicitConversions
+import  scala.language.{implicitConversions, postfixOps}
 
 /** Generators for the miscutils module configurations. */
 package object generators {
@@ -29,14 +29,21 @@ package object generators {
   /** A Limited[Int] representing bit widths. */
   type BitWidth = Limited[Int]
   def bitWidthGen(max: Int = 64): Gen[BitWidth] = genLimited(1, max)
-  /** A Limited[Int] representing data sizes. */
+  object BitWidth { def apply(w: Int)(implicit max: Int = 64): BitWidth = Limited(w, 1, max) }
+
+  /** A Limited[Int] representing (non-empty) data sizes. */
   type DataSize = Limited[Int]
   def dataSizeGen(max: Int = 1024): Gen[DataSize] = genLimited(1, max)
+  object DataSize { def apply(s: Int)(implicit max: Int = 1024): BitWidth = Limited(s, 1, max) }
+
+  /** Computes all integer multiples and fractions of inW between 1 and inW.max. */
+  def validConversionWidths(inW: BitWidth): Set[BitWidth] =
+    (Stream.from(2) map (inW * _) takeWhile (_ <= inW.max) toSet) ++
+    (Stream.from(2) map (inW / _) takeWhile (_ > 0) filter (inW % _ == 0) toSet) map (BitWidth(_))
 
   /** Generates bit width that is a integer ratio from the other. */
   def conversionWidthGen(inW: BitWidth): Gen[BitWidth] = Gen.oneOf(
-    ((Stream.from(2) map (inW * _) takeWhile ((i: Int) => i <= inW.max)).toList ++
-     (Stream.from(2) map (inW / _) takeWhile ((i: Int) => i > 0) filter ((i: Int) => inW % i == 0)).toList).map(Limited(_, 1, 64))
+    validConversionWidths(inW).toSeq
   )
 
   /** Generator for a DataWidthConverter test configuration consisting of