Add ACKs to interrupts

common/ip/MSIXIntrCtrl/component.xml

@@ -336,7 +336,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>f5bf6125</spirit:value>
+            <spirit:value>09ee8702</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -352,7 +352,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>ec2e46f0</spirit:value>
+            <spirit:value>a1f70f90</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -879,8 +879,6 @@
       <spirit:file>
         <spirit:name>constraints/msix_intr_ctrl.xdc</spirit:name>
         <spirit:userFileType>xdc</spirit:userFileType>
-        <spirit:userFileType>USED_IN_implementation</spirit:userFileType>
-        <spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
         <spirit:define>
           <spirit:name>processing_order</spirit:name>
           <spirit:value>late</spirit:value>
@@ -905,7 +903,7 @@
       <spirit:file>
         <spirit:name>src/mkMSIXIntrCtrl.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_b020e4f8</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_f42c23cf</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -977,16 +975,16 @@
       <xilinx:displayName>MSIXIntrCtrl</xilinx:displayName>
       <xilinx:definitionSource>package_project</xilinx:definitionSource>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2019-01-25T10:19:28Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2019-03-27T13:22:48Z</xilinx:coreCreationDateTime>
       <xilinx:tags>
         <xilinx:tag xilinx:name="nopcore"/>
       </xilinx:tags>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2017.4</xilinx:xilinxVersion>
+      <xilinx:xilinxVersion>2018.3</xilinx:xilinxVersion>
       <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="005537d1"/>
       <xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="ce939530"/>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="41a46aaf"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="628e2b97"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="9334f89d"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="4ff74fe2"/>
     </xilinx:packagingInfo>

tlkm/pcie/pcie_irq.c

@@ -21,10 +21,13 @@ irqreturn_t tlkm_pcie_slot_irq_ ## nr(int irq, void *dev_id) 		\
 { 									\
 	struct pci_dev *pdev = (struct pci_dev *)dev_id; \
 	struct tlkm_pcie_device *dev = (struct tlkm_pcie_device *) dev_get_drvdata(&pdev->dev); \
+	struct platform *p = &dev->parent->cls->platform;\
+	volatile uint32_t* msix_ack = (volatile uint32_t*) (dev->parent->mmap.plat + ((0x500000 + 0x8120) - p->plat.base)); \
 	BUG_ON(! dev); \
 	if (! schedule_work(&dev->irq_work[nr])) \
 		tlkm_perfc_irq_error_already_pending_inc(dev->parent->dev_id); \
 	tlkm_perfc_total_irqs_inc(dev->parent->dev_id); \
+	msix_ack[0] = nr + pcie_cls.npirqs; \
 	return IRQ_HANDLED; \
 }