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tapasco
tapasco
Commits
5702af68
Commit
5702af68
authored
Aug 25, 2017
by
Jens Korinth
Browse files
Bugfix concerning log2Ceil(1) == 0
parent
a09d132d
Changes
3
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Inline
Side-by-side
src/test/scala/datawidthconverter/CorrectnessHarness.scala
View file @
5702af68
...
...
@@ -23,7 +23,7 @@ class CorrectnessHarness(inWidth: Int,
delay
:
Int
=
10
)
extends
Module
{
require
(
delay
>
0
,
"delay bitwidth must be > 0"
)
val
io
=
IO
(
new
Bundle
{
val
dly
=
Input
(
UInt
(
log2Ceil
(
delay
).
W
))
val
dly
=
Input
(
UInt
(
Seq
(
log2Ceil
(
delay
)
,
1
).
max
.
W
))
val
dsrc_out_valid
=
Output
(
Bool
())
val
dsrc_out_bits
=
Output
(
UInt
())
val
dwc_inq_valid
=
Output
(
Bool
())
...
...
src/test/scala/datawidthconverter/DataWidthConverterSpec.scala
View file @
5702af68
...
...
@@ -9,16 +9,16 @@ class DataWidthConverterSpec extends ChiselFlatSpec with Checkers {
behavior
of
"DataWidthConverter"
it
should
"preserve data integrity in arbitrary conversions"
in
check
(
forAll
(
bitWidthGen
(
64
),
Arbitrary
.
arbitrary
[
Boolean
],
genLimited
(
1
,
1
00
))
{
check
(
forAll
(
bitWidthGen
(
64
),
Arbitrary
.
arbitrary
[
Boolean
],
genLimited
(
1
,
1
5
))
{
case
(
inW
,
littleEndian
,
delay
)
=>
forAll
(
conversionWidthGen
(
inW
))
{
outW
=>
println
(
"Testing bitwidth conversion from %d bits -> %d bits (%s) with %d delay"
.
format
(
inW
:
Int
,
outW
:
Int
,
if
(
littleEndian
)
"little-endian"
else
"big-endian"
,
delay
:
Int
))
Driver
.
execute
(
Array
(
"--fint-write-vcd"
,
"--target-dir"
,
"test/DataWidthConverter"
),
()
=>
new
CorrectnessHarness
(
inW
,
outW
,
littleEndian
,
delay
))
()
=>
new
CorrectnessHarness
(
inW
,
outW
,
littleEndian
,
1
))
{
m
=>
new
CorrectnessTester
(
m
)
}
}
})
}
,
minSuccessful
(
25
)
)
it
should
"transfer data with minimal delays"
in
check
(
forAll
(
bitWidthGen
(
64
),
Arbitrary
.
arbitrary
[
Boolean
])
{
case
(
inW
,
littleEndian
)
=>
...
...
src/test/scala/datawidthconverter/MinimalDelayTester.scala
View file @
5702af68
...
...
@@ -31,7 +31,7 @@ class MinimalDelayTester[T <: UInt](m: MinimalDelayHarness) extends PeekPokeTest
if
(
peek
(
m
.
io
.
dsrc_out_valid
)
>
0
&&
peek
(
m
.
io
.
dwc_inq_ready
)
>
0
)
{
val
e
=
peek
(
m
.
io
.
dsrc_out_bits
)
expecteds
=
expecteds
:+
e
println
(
"adding expected value: %d (%s)"
.
format
(
e
,
toBinaryString
(
e
,
m
.
dwc
.
inWidth
)))
//
println ("adding expected value: %d (%s)".format(e, toBinaryString(e, m.dwc.inWidth)))
}
// check output element: must match head of expecteds
...
...
@@ -45,7 +45,7 @@ class MinimalDelayTester[T <: UInt](m: MinimalDelayHarness) extends PeekPokeTest
expect
(
false
,
errmsg
)
}
else
{
if
(
v
==
expecteds
.
head
)
{
println
(
"element #%d ok!"
.
format
(
i
))
//
println ("element #%d ok!".format(i))
}
else
{
val
errmsg
=
"element #%d wrong: expected %d (%s), found %d (%s)"
.
format
(
i
,
expecteds
.
head
,
toBinaryString
(
expecteds
.
head
,
m
.
dwc
.
inWidth
),
...
...
Jens Korinth
@jk
mentioned in commit
17f0d672
·
Mar 05, 2018
mentioned in commit
17f0d672
mentioned in commit 17f0d67240ebf5d7e1d0be9162d272b04256c47d
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