Minimize SignalGenerator

*  direct reference of reset is discouraged
*  replaced explicit reset code with RegInits

src/main/scala/SignalGenerator.scala

@@ -31,29 +31,22 @@ class SignalGenerator(val signals: SignalGenerator.Waveform,
   val io = IO(new SignalGenerator.IO)
   val cnts_rom = Vec(signals map (n => (n.periods - 1).U))
   val vals_rom = Vec(signals map (n => (n.value).B))
-  val cnt      = Reg(UInt(log2Ceil(signals.max.periods).W))
-  val curr_idx = Reg(UInt(log2Ceil(signals.length).W))
-  val vreg     = Reg(Bool())
+  val cnt      = RegInit(UInt(log2Ceil(signals.max.periods).W), init = cnts_rom(0))
+  val curr_idx = RegInit(UInt(log2Ceil(signals.length).W), init = 0.U)
+  val vreg     = RegInit(Bool(), init = vals_rom(0))
 
   io.v := vreg
 
-  when (reset) {
-    curr_idx := 0.U
-    cnt      := cnts_rom(0)
-    vreg     := vals_rom(0)
-  }
-  .otherwise {
-    vreg := vals_rom(curr_idx)
-    // trigger on either clock or pos input edge
-    when (if (useInputAsClock) io.in && !RegNext(io.in) else true.B) {
-      when (cnt === 0.U) {
-        val next_idx = Mux(curr_idx < (signals.length - 1).U, curr_idx + 1.U, 0.U)
-        curr_idx    := next_idx
-        cnt         := cnts_rom(next_idx)
-      }
-      .otherwise {
-        cnt := cnt - 1.U
-      }
+  vreg := vals_rom(curr_idx)
+  // trigger on either clock or pos input edge
+  when (if (useInputAsClock) io.in && !RegNext(io.in) else true.B) {
+    when (cnt === 0.U) {
+      val next_idx = Mux(curr_idx < (signals.length - 1).U, curr_idx + 1.U, 0.U)
+      curr_idx    := next_idx
+      cnt         := cnts_rom(next_idx)
+    }
+    .otherwise {
+      cnt := cnt - 1.U
     }
   }
 }

src/test/scala/signalgenerator/SignalGeneratorSpec.scala

@@ -10,9 +10,9 @@ import  scala.util.Random
 
 /** Connects a random clock signal generator to the main signal generator to test
  *  external clock port facilities.
- */
+ **/
 class SignalGeneratorWithClockInput(val signals: Waveform) extends Module {
-  val io = IO(new Bundle { val v = Output(Bool()); val clk = Output(Bool()) })
+  val io  = IO(new Bundle { val v = Output(Bool()); val clk = Output(Bool()) })
   val clw = 0 to signals.length * 2 map (i => Signal(i % 2 == 0, 2 + Random.nextInt().abs % 10))
   val clk = Module(new SignalGenerator(clw))
   val sgn = Module(new SignalGenerator(signals, true))