Commit 5d7f8f30 authored by Jens Korinth's avatar Jens Korinth
Browse files

Closes #136: Full Slave Wrapper: Support multiple slave ports

parent 7a96aa1a
......@@ -26,7 +26,7 @@ namespace eval full_axi_wrapper {
# check interfaces: AXI3/AXI4 slaves will be wrappped
set inst [get_bd_cells $inst]
set full_slave_ifs [get_bd_intf_pins -of_objects $inst -filter {MODE == Slave && (CONFIG.PROTOCOL == AXI3 || CONFIG.PROTOCOL == AXI4)}]
if {[llength $full_slave_ifs] > 1} { error "full_axi_wrapper plugin: Found [llength $full_slave_ifs] full slave interfaces, this is not supported at the moment" }
# if {[llength $full_slave_ifs] > 1} { error "full_axi_wrapper plugin: Found [llength $full_slave_ifs] full slave interfaces, this is not supported at the moment" }
if {[llength $full_slave_ifs] > 0} {
puts " IP has full slaves, will add protocol converter"
puts " found full slave interfaces: $full_slave_ifs"
......@@ -40,11 +40,26 @@ namespace eval full_axi_wrapper {
set ninst [get_bd_cells $group/internal_$name]
current_bd_instance $group
# create slave ports
set saxi_port [create_bd_intf_pin -vlnv "xilinx.com:interface:aximm_rtl:1.0" -mode Slave "S_AXI_LITE"]
set conv [tapasco::createProtocolConverter "conv" "AXI4LITE" [get_property CONFIG.PROTOCOL $full_slave_ifs]]
# rewire full slaves
set si 0
foreach fs $full_slave_ifs {
# create slave port
set saxi_port [create_bd_intf_pin -vlnv "xilinx.com:interface:aximm_rtl:1.0" -mode Slave "S_AXI_LITE_$si"]
set conv [tapasco::createProtocolConverter "conv_$si" "AXI4LITE" [get_property CONFIG.PROTOCOL $fs]]
connect_bd_intf_net $saxi_port [get_bd_intf_pins -of_objects $conv -filter {MODE == Slave}]
connect_bd_intf_net [get_bd_intf_pins -filter {MODE == Master} -of_objects $conv] $full_slave_ifs
connect_bd_intf_net [get_bd_intf_pins -filter {MODE == Master} -of_objects $conv] $fs
incr si
}
# bypass existing AXI4Lite slaves
set lite_ports [list]
set lites [get_bd_intf_pins -of_objects $inst -filter {MODE == Slave && CONFIG.PROTOCOL == AXI4LITE}]
foreach ls $lites {
set op [create_bd_intf_pin -vlnv "xilinx.com:interface:aximm_rtl:1.0" -mode Slave [get_property NAME $ls]]
connect_bd_intf_net $op $ls
lappend lite_ports $ls
}
puts "lite_ports = $lite_ports"
# create master ports
set maxi_ports [list]
......
set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVCMOS33} [get_ports sys_clk]
create_clock -period 8.000 -name sys_clk_pin -waveform {0.000 4.000} -add [get_ports sys_clk]
create_debug_core u_ila_0 ila
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU_CNT 2 [get_debug_cores u_ila_0]
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0]
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
set_property port_width 1 [get_debug_ports u_ila_0/clk]
connect_debug_port u_ila_0/clk [get_nets [list system_i/ClockResets/clk_wiz/inst/clk_out1]]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
set_property port_width 1 [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list system_i/InterruptControl_irq_out]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
set_property port_width 1 [get_debug_ports u_ila_0/probe1]
connect_debug_port u_ila_0/probe1 [get_nets [list system_i/uArch_irq_0]]
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets u_ila_0_clk_out1]
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