Commit 642f59a7 authored by Jaco Hofmann's avatar Jaco Hofmann
Browse files

Use design clock to drive network related IP

parent 7ef8a06c
......@@ -10,6 +10,10 @@
set tx_pins_p {"A6" "B8" "C6" "D8"}
set locations {"GTHE2_CHANNEL_X1Y39" "GTHE2_CHANNEL_X1Y38" "GTHE2_CHANNEL_X1Y37" "GTHE2_CHANNEL_X1Y36"}
set design_clk [tapasco::subsystem::get_port "design" "clk"]
set design_clk_aresetn [tapasco::subsystem::get_port "design" "rst" "peripheral" "resetn"]
set design_clk_areset [tapasco::subsystem::get_port "design" "rst" "peripheral" "reset"]
set networkStreams [get_bd_intf_pins -filter {NAME =~ "*sfp_axis_*rx*"} -of_objects [get_bd_cells /arch/target_ip_*]]
set networkIPs [list]
......@@ -76,8 +80,20 @@
puts $constraints_file {set_property PACKAGE_PIN BA29 [get_ports {resetClock_0}]}
puts $constraints_file {set_property IOSTANDARD LVCMOS18 [get_ports {resetClock_0}]}
puts $constraints_file {set_property PACKAGE_PIN G13 [get_ports {led_0}]}
puts $constraints_file {set_property IOSTANDARD LVCMOS15 [get_ports {led_0}]}
puts $constraints_file {set_property PACKAGE_PIN G13 [get_ports {led_clock_0}]}
puts $constraints_file {set_property IOSTANDARD LVCMOS15 [get_ports {led_clock_0}]}
puts $constraints_file {set_property PACKAGE_PIN L15 [get_ports {led_init_done_0}]}
puts $constraints_file {set_property IOSTANDARD LVCMOS15 [get_ports {led_init_done_0}]}
puts $constraints_file {set_property PACKAGE_PIN AR22 [get_ports {mmcm_locked_0}]}
puts $constraints_file {set_property IOSTANDARD LVCMOS15 [get_ports {mmcm_locked_0}]}
puts $constraints_file {set_property PACKAGE_PIN AR23 [get_ports {init_calib_complete_0}]}
puts $constraints_file {set_property IOSTANDARD LVCMOS15 [get_ports {init_calib_complete_0}]}
puts $constraints_file {set_property PACKAGE_PIN BB12 [get_ports {reprogram_do_reprogram_0}]}
puts $constraints_file {set_property IOSTANDARD LVCMOS15 [get_ports {reprogram_do_reprogram_0}]}
puts "Adding required external ports"
create_bd_port -dir I gt_refclk_clk_p
......@@ -85,12 +101,15 @@
set_property CONFIG.FREQ_HZ 156250000 [get_bd_ports /gt_refclk_clk_p]
set_property CONFIG.FREQ_HZ 156250000 [get_bd_ports /gt_refclk_clk_n]
set si5324prog [create_bd_cell -type ip -vlnv esa.informatik.tu-darmstadt.de:user:SumeClockProgrammer:1.0 "SI5324Prog"]
puts "Instantiating clock wizard for 100MHz dclk"
set dclk_wiz [tapasco::ip::create_clk_wiz dclk_wiz]
set_property -dict [list CONFIG.USE_SAFE_CLOCK_STARTUP {true} CONFIG.CLKOUT1_REQUESTED_OUT_FREQ 100 \
CONFIG.USE_LOCKED {false} \
CONFIG.USE_RESET {false}] $dclk_wiz
connect_bd_net [get_bd_pins mem_clk] [get_bd_pins $dclk_wiz/clk_in1]
CONFIG.USE_RESET {true}] $dclk_wiz
connect_bd_net $design_clk_areset [get_bd_pins $dclk_wiz/reset]
connect_bd_net $design_clk [get_bd_pins $dclk_wiz/clk_in1]
set slow_clk [get_bd_pins $dclk_wiz/clk_out1]
for {set i 0} {$i < [llength $networkIPs]} {incr i} {
......@@ -123,13 +142,13 @@
connect_bd_net [get_bd_pins sfpmac_0/coreclk_out] [get_bd_pins sfpmac_${i}/coreclk]
connect_bd_net [get_bd_pins sfpmac_0/gttxreset_out] [get_bd_pins sfpmac_${i}/gttxreset]
connect_bd_net [get_bd_pins sfpmac_0/gtrxreset_out] [get_bd_pins sfpmac_${i}/gtrxreset]
connect_bd_net [get_bd_pins mem_peripheral_areset] [get_bd_pins sfpmac_${i}/areset]
connect_bd_net $design_clk_areset [get_bd_pins sfpmac_${i}/areset]
connect_bd_net [get_bd_pins sfpmac_${i}/areset_coreclk] [get_bd_pins sfpmac_0/gttxreset_out]
} else {
set_property -dict [list CONFIG.base_kr {BASE-R} CONFIG.SupportLevel {1} CONFIG.autonegotiation {0} CONFIG.fec {0} CONFIG.Statistics_Gathering {0} CONFIG.Statistics_Gathering {false} CONFIG.TransceiverControl {true} CONFIG.DRP {false}] [get_bd_cells sfpmac_${i}]
connect_bd_net [get_bd_ports /gt_refclk_clk_p] [get_bd_pins sfpmac_${i}/refclk_p]
connect_bd_net [get_bd_ports /gt_refclk_clk_n] [get_bd_pins sfpmac_${i}/refclk_n]
connect_bd_net [get_bd_pins sfpmac_${i}/reset] [get_bd_pins mem_peripheral_areset]
connect_bd_net $design_clk_areset [get_bd_pins sfpmac_${i}/reset]
#puts $constraints_file_late {set_false_path -from [get_clocks -of_objects [get_pins system_i/Network/sfpmac_0/coreclk_out]] -to [get_clocks -of_objects [get_pins system_i/Resets/design_aclk]]}
#puts $constraints_file_late {set_false_path -from [get_clocks -of_objects [get_pins system_i/Resets/design_aclk]] -to [get_clocks -of_objects [get_pins system_i/Network/sfpmac_0/coreclk_out]]}
......@@ -187,9 +206,6 @@
}
puts $constraints_file {set_property PACKAGE_PIN G13 [get_ports clockled]}
puts $constraints_file {set_property IOSTANDARD LVCMOS15 [get_ports clockled]}
close $constraints_file
read_xdc $constraints_fn
set_property PROCESSING_ORDER EARLY [get_files $constraints_fn]
......@@ -198,8 +214,6 @@
read_xdc $constraints_fn_late
set_property PROCESSING_ORDER LATE [get_files $constraints_fn_late]
set si5324prog [create_bd_cell -type ip -vlnv esa.informatik.tu-darmstadt.de:user:SumeClockProgrammer:1.0 "SI5324Prog"]
make_bd_pins_external [get_bd_pins $si5324prog/SDA]
make_bd_pins_external [get_bd_pins $si5324prog/SCL]
......@@ -207,16 +221,24 @@
set rst_gen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 "dclk_reset"]
connect_bd_net [get_bd_pins $rst_gen/slowest_sync_clk] $slow_clk
connect_bd_net [get_bd_pins mem_peripheral_areset] [get_bd_pins $rst_gen/ext_reset_in]
connect_bd_net $design_clk_aresetn [get_bd_pins $rst_gen/ext_reset_in]
connect_bd_net [get_bd_pins $rst_gen/peripheral_aresetn] [get_bd_pins $si5324prog/RST_N]
make_bd_pins_external [get_bd_pins $si5324prog/resetSwitch]
make_bd_pins_external [get_bd_pins $si5324prog/resetClock]
make_bd_pins_external [get_bd_pins $si5324prog/led]
make_bd_pins_external [get_bd_pins $si5324prog/led_clock]
make_bd_pins_external [get_bd_pins $si5324prog/led_init_done]
make_bd_pins_external [get_bd_pins $si5324prog/reprogram_do_reprogram]
connect_bd_net [get_bd_pins sfpmac_0/coreclk_out] [get_bd_pins $si5324prog/CLK_gt_clk]
connect_bd_net [get_bd_pins $rst_inv/Res] [get_bd_pins $si5324prog/RST_N_gt_rst_n]
set inst [current_bd_instance .]
current_bd_instance
make_bd_pins_external [get_bd_pins memory/mig/mmcm_locked]
make_bd_pins_external [get_bd_pins memory/mig/init_calib_complete]
current_bd_instance $inst
#set ila [create_bd_cell -type ip -vlnv xilinx.com:ip:system_ila:1.1 "net_ila"]
#set_property -dict [list CONFIG.C_DATA_DEPTH {8192} CONFIG.C_NUM_OF_PROBES {6} CONFIG.C_EN_STRG_QUAL {1} CONFIG.C_PROBE3_MU_CNT {2} CONFIG.C_PROBE2_MU_CNT {2} CONFIG.C_PROBE1_MU_CNT {2} CONFIG.C_PROBE0_MU_CNT {2} CONFIG.ALL_PROBE_SAME_MU_CNT {2} CONFIG.C_MON_TYPE {NATIVE}] $ila
......
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