Commit 68639fbe authored by Jens Korinth's avatar Jens Korinth
Browse files

Add System ILA support to common Tcl

* remove support for 2016.2, 2016.3
parent 58a83c52
......@@ -480,6 +480,26 @@ namespace eval tapasco {
return $inst
}
# Instantiates a System ILA core for AXI debugging.
# @param name Name of the instance
# @param ports Number of ports (optional, default: 1)
# @param depth Data depth (optional, default: 1024)
# @param stages Input pipeline stages (optional, default: 0)
# @return block design cell (or error)
proc createSystemILA {name {ports 1} {depth 1024} {stages 0}} {
variable stdcomps
puts "Creating System ILA $name ..."
set vlnv [dict get $stdcomps system_ila vlnv]
puts " VLNV: $vlnv"
set inst [create_bd_cell -type ip -vlnv $vlnv $name]
set_property -dict [list \
CONFIG.C_NUM_MONITOR_SLOTS $ports \
CONFIG.C_DATA_DEPTH $depth \
CONFIG.C_INPUT_PIPE_STAGES $stages \
] $inst
return $inst
}
# Returns the interface pin groups for all AXI MM interfaces on cell.
# @param cell the object whose interfaces shall be returned
# @parma mode filters interfaces by mode (default: Master)
......
# create a dictionary of compatible VLNVs
dict set stdcomps axi_ic vlnv "xilinx.com:ip:axi_interconnect:2.1"
dict set stdcomps ps vlnv "xilinx.com:ip:processing_system7:5.5"
dict set stdcomps ps_bfm vlnv "xilinx.com:ip:processing_system7_bfm:2.0"
dict set stdcomps axi_irqc vlnv "xilinx.com:ip:axi_intc:4.1"
dict set stdcomps axi_cache vlnv "xilinx.com:ip:system_cache:3.0"
dict set stdcomps xlconcat vlnv "xilinx.com:ip:xlconcat:2.1"
dict set stdcomps xlslice vlnv "xilinx.com:ip:xlslice:1.0"
dict set stdcomps xlconst vlnv "xilinx.com:ip:xlconstant:1.1"
dict set stdcomps rst_gen vlnv "xilinx.com:ip:proc_sys_reset:5.0"
dict set stdcomps proto_conv vlnv "xilinx.com:ip:axi_protocol_converter:2.1"
dict set stdcomps bincnt vlnv "xilinx.com:ip:c_counter_binary:12.0"
dict set stdcomps dualdma vlnv "esa.informatik.tu-darmstadt.de:user:dual_dma:1.4"
dict set stdcomps oled_ctrl vlnv "esa.cs.tu-darmstadt.de:user:oled_pc:1.0"
dict set stdcomps mm_to_lite vlnv "esa.cs.tu-darmstadt.de:user:mm_to_lite:1.0"
dict set stdcomps system_cache vlnv "xilinx.com:ip:system_cache:3.1"
dict set stdcomps mig_core vlnv "xilinx.com:ip:mig_7series:4.0"
dict set stdcomps axi_pcie3_0 vlnv "xilinx.com:ip:axi_pcie3:2.1"
dict set stdcomps tapasco_status vlnv "esa.cs.tu-darmstadt.de:user:tapasco_status:1.1"
dict set stdcomps clk_wiz "xilinx.com:ip:clk_wiz:5.3"
dict set stdcomps msix_intr_ctrl vlnv "esa.informatik.tu-darmstadt.de:user:MSIXIntrCtrl:1.0"
dict set stdcomps axi_reg_slice vlnv "xilinx.com:ip:axi_register_slice:2.1"
dict set stdcomps dwidth_conv vlnv "xilinx.com:ip:axi_dwidth_converter:2.1"
# create a dictionary of compatible VLNVs
dict set stdcomps axi_ic vlnv "xilinx.com:ip:axi_interconnect:2.1"
dict set stdcomps ps vlnv "xilinx.com:ip:processing_system7:5.5"
dict set stdcomps ps_bfm vlnv "xilinx.com:ip:processing_system7_bfm:2.0"
dict set stdcomps axi_irqc vlnv "xilinx.com:ip:axi_intc:4.1"
dict set stdcomps axi_cache vlnv "xilinx.com:ip:system_cache:3.0"
dict set stdcomps xlconcat vlnv "xilinx.com:ip:xlconcat:2.1"
dict set stdcomps xlslice vlnv "xilinx.com:ip:xlslice:1.0"
dict set stdcomps xlconst vlnv "xilinx.com:ip:xlconstant:1.1"
dict set stdcomps rst_gen vlnv "xilinx.com:ip:proc_sys_reset:5.0"
dict set stdcomps proto_conv vlnv "xilinx.com:ip:axi_protocol_converter:2.1"
dict set stdcomps bincnt vlnv "xilinx.com:ip:c_counter_binary:12.0"
dict set stdcomps dualdma vlnv "esa.informatik.tu-darmstadt.de:user:dual_dma:1.5"
dict set stdcomps oled_ctrl vlnv "esa.cs.tu-darmstadt.de:user:oled_pc:1.0"
dict set stdcomps mm_to_lite vlnv "esa.cs.tu-darmstadt.de:user:mm_to_lite:1.0"
dict set stdcomps system_cache vlnv "xilinx.com:ip:system_cache:3.1"
dict set stdcomps mig_core vlnv "xilinx.com:ip:mig_7series:4.0"
dict set stdcomps axi_pcie3_0 vlnv "xilinx.com:ip:axi_pcie3:3.0"
dict set stdcomps tapasco_status vlnv "esa.cs.tu-darmstadt.de:user:tapasco_status:1.1"
dict set stdcomps clk_wiz "xilinx.com:ip:clk_wiz:5.3"
dict set stdcomps msix_intr_ctrl vlnv "esa.informatik.tu-darmstadt.de:user:MSIXIntrCtrl:1.0"
dict set stdcomps axi_reg_slice vlnv "xilinx.com:ip:axi_register_slice:2.1"
dict set stdcomps dwidth_conv vlnv "xilinx.com:ip:axi_dwidth_converter:2.1"
......@@ -21,3 +21,4 @@ dict set stdcomps clk_wiz "xilinx.com:ip:clk_wiz:5.3"
dict set stdcomps msix_intr_ctrl vlnv "esa.informatik.tu-darmstadt.de:user:MSIXIntrCtrl:1.0"
dict set stdcomps axi_reg_slice vlnv "xilinx.com:ip:axi_register_slice:2.1"
dict set stdcomps dwidth_conv vlnv "xilinx.com:ip:axi_dwidth_converter:2.1"
dict set stdcomps system_ila vlnv "xilinx.com:ip:system_ila:1.0"
......@@ -21,3 +21,4 @@ dict set stdcomps clk_wiz "xilinx.com:ip:clk_wiz:5.4"
dict set stdcomps msix_intr_ctrl vlnv "esa.informatik.tu-darmstadt.de:user:MSIXIntrCtrl:1.0"
dict set stdcomps axi_reg_slice vlnv "xilinx.com:ip:axi_register_slice:2.1"
dict set stdcomps dwidth_conv vlnv "xilinx.com:ip:axi_dwidth_converter:2.1"
dict set stdcomps system_ila vlnv "xilinx.com:ip:system_ila:1.0"
......@@ -21,3 +21,5 @@ dict set stdcomps clk_wiz "xilinx.com:ip:clk_wiz:5.4"
dict set stdcomps msix_intr_ctrl vlnv "esa.informatik.tu-darmstadt.de:user:MSIXIntrCtrl:1.0"
dict set stdcomps axi_reg_slice vlnv "xilinx.com:ip:axi_register_slice:2.1"
dict set stdcomps dwidth_conv vlnv "xilinx.com:ip:axi_dwidth_converter:2.1"
dict set stdcomps dwidth_conv vlnv "xilinx.com:ip:axi_dwidth_converter:2.1"
dict set stdcomps system_ila vlnv "xilinx.com:ip:system_ila:1.0"
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