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tapasco
tapasco
Commits
6f84679d
Commit
6f84679d
authored
Sep 22, 2017
by
Jens Korinth
Browse files
Merge chisel-miscutils
Merge commit '48f930ee8d5d702ff5b29577c8dc13aef4b5363d'
parents
b351de03
c734b464
Changes
3
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Inline
Side-by-side
miscutils/src/main/scala/DecoupledDataSource.scala
View file @
6f84679d
...
...
@@ -33,9 +33,9 @@ class DecoupledDataSource[T <: Data](gen: T,
val
rom
=
Vec
.
tabulate
(
size
)(
n
=>
ds
(
n
))
// ROM with data
io
.
out
.
bits
:=
rom
(
i
)
// current index data
io
.
out
.
valid
:=
i
<
size
.
U
// valid until exceeded
io
.
out
.
valid
:=
repeat
.
B
|
i
<
size
.
U
// valid until exceeded
when
(
io
.
out
.
ready
&&
io
.
out
.
valid
)
{
when
(
io
.
out
.
fire
()
)
{
val
next
=
if
(
repeat
)
{
if
(
math
.
pow
(
2
,
log2Ceil
(
size
)).
toInt
==
size
)
i
+
1.
U
...
...
miscutils/src/test/scala/datawidthconverter/MinimalDelayHarness.scala
View file @
6f84679d
...
...
@@ -38,7 +38,7 @@ class MinimalDelayHarness(val inWidth: Int,
val
dwc2
=
Module
(
new
DataWidthConverter
(
outWidth
,
inWidth
,
littleEndian
))
dwc
.
io
.
inq
<>
dsrc
.
io
.
out
dwc2
.
io
.
inq
<>
dwc
.
io
.
deq
dwc2
.
io
.
deq
.
ready
:=
!
reset
dwc2
.
io
.
deq
.
ready
:=
RegNext
(
true
.
B
,
init
=
false
.
B
)
// internal peek-and-poke does not work, need to wire as outputs:
io
.
dsrc_out_valid
:=
dsrc
.
io
.
out
.
valid
...
...
miscutils/src/test/scala/decoupleddatasource/DecoupledDataSourceSpec.scala
View file @
6f84679d
...
...
@@ -19,7 +19,7 @@ class OutputCheck[T <: UInt](m: DecoupledDataSource[T], data: Int => Int) extend
reset
(
10
)
poke
(
m
.
io
.
out
.
ready
,
true
)
var
i
=
0
while
(
peek
(
m
.
io
.
out
.
valid
)
>
0
&
&
i
<=
m
.
size
)
{
while
(
peek
(
m
.
io
.
out
.
valid
)
>
0
&
i
<=
m
.
size
)
{
if
(
i
>=
m
.
size
)
{
expect
(
m
.
repeat
,
"repeat is false, but index (%d) exceeds size(%d)"
.
format
(
i
,
m
.
size
))
// :: errors
}
else
{
...
...
Jens Korinth
@jk
mentioned in commit
17f0d672
·
Mar 05, 2018
mentioned in commit
17f0d672
mentioned in commit 17f0d67240ebf5d7e1d0be9162d272b04256c47d
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