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tapasco
tapasco
Commits
74a12ddd
Commit
74a12ddd
authored
May 02, 2022
by
Carsten Heinz
Browse files
Fix off-by-one error in versal address ignore list
parent
27ee2318
Pipeline
#2566
passed with stages
in 209 minutes and 17 seconds
Changes
1
Pipelines
1
Show whitespace changes
Inline
Side-by-side
toolflow/vivado/platform/versal/versal_base.tcl
View file @
74a12ddd
...
...
@@ -482,7 +482,7 @@
# skip i = 0, 1
(
those are managed by tapasco
)
for
{
set j 0
}
{
$j
< 4
}
{
incr j
}
{
lappend ignored
"/memory/axi_noc_0/S0
${i}
_AXI/C
${j}
_DDR_LOW3"
for
{
set k
0
}
{
$k
<
4
}
{
incr k
}
{
for
{
set k
1
}
{
$k
<
5
}
{
incr k
}
{
lappend ignored
"/memory/axi_noc_0/S0
${i}
_AXI/C
${j}
_DDR_LOW3x
${k}
"
}
}
...
...
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