Commit 793c88df authored by Jens Korinth's avatar Jens Korinth
Browse files

Fix bug concerning too narrow address widths in RegisterFile

* arbitrary configs would sometimes mandate less bits for the address
  than required by the register map
* could be fixed in the register map generator, but I opted to fix it by
  permanently widening the address to 32 bits (sufficient for all cases)
parent 4286de8c
......@@ -27,7 +27,7 @@ object RegisterFile {
require (regs.size == 1 || !(o map (_._2) reduce (_ || _)), "ranges must not overlap: " + regs)
/** Minimum bit width of address lines. */
lazy val minAddrWidth: AddrWidth = AddrWidth(Seq(if (regs.size * axi.dataWidth.toInt >= regs.keys.max) {
lazy val minAddrWidth: AddrWidth = AddrWidth(Seq(if (regs.size * axi.dataWidth.toInt / addressWordBits >= regs.keys.max) {
log2Ceil((regs.size * axi.dataWidth.toInt) / addressWordBits)
} else {
log2Ceil(regs.keys.max)
......@@ -55,7 +55,7 @@ object RegisterFile {
**/
class IO(cfg: Configuration)(implicit axi: Axi4Lite.Configuration) extends Bundle {
val addrWidth: AddrWidth = AddrWidth(Seq(cfg.minAddrWidth:Int, axi.addrWidth:Int).max)
val saxi = Axi4Lite.Slave(axi)
val saxi = Axi4Lite.Slave(axi.copy(addrWidth = addrWidth))
override def cloneType = new IO(cfg)(axi).asInstanceOf[this.type]
}
......@@ -78,6 +78,7 @@ class RegisterFile(cfg: RegisterFile.Configuration)
override def cloneType = (new ReadData).asInstanceOf[this.type]
}
cinfo(s"AXI config: $axi")
val io = IO(new RegisterFile.IO(cfg))
// workaround: code below does not work due to optional elements in bundle
......
......@@ -59,7 +59,7 @@ class RegisterFileSpec extends ChiselFlatSpec with Checkers {
val args = chiselArgs ++ Array("--target-dir", testDir)
val actions = generateActionsFromRegMap(regs)
Driver.execute(args, () => new RegFileTest(regs.size, width / 8, regs filter { case (_, or) => or.nonEmpty } map { case (i, or) => (i, or.get) }, actions))
{ m => new GenericTester(width, regs, m) } // FIXME implement generic Tester
{ m => new GenericTester(width, regs, m) }
}
private class GenericTester(width: DataWidth, regs: Map[Int, Option[ControlRegister]], m: RegFileTest) extends PeekPokeTester(m) {
......@@ -147,10 +147,13 @@ class RegisterFileSpec extends ChiselFlatSpec with Checkers {
}}
}
"random register files" should "behave as expected at each register" in {
check(forAll(chisel.axi.generators.Axi4Lite.configurationGen) { cfg => {
implicit val axi = cfg
forAll(dataWidthGen) { w => forAllNoShrink(registerMapGen(w)) { regs => genericTest(w, regs) } }
}})
}
behavior of "RegisterFile"
it should "behave correctly for arbitrary configurations" in
check(forAll(chisel.axi.generators.Axi4Lite.configurationGen) { cfg =>
forAllNoShrink(registerMapGen(cfg.dataWidth)) { regs =>
implicit val axi = cfg.copy(addrWidth = chisel.axi.AddrWidth(32))
genericTest(cfg.dataWidth, regs)
}
}, minSuccessful(100))
}
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