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tapasco
tapasco
Commits
7acd060d
Commit
7acd060d
authored
Feb 16, 2018
by
Jens Korinth
Browse files
Increase default target frequency in Import to 1GHz
parent
2dbe1061
Pipeline
#288
passed with stage
in 3 minutes and 8 seconds
Changes
1
Pipelines
1
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Inline
Side-by-side
src/main/scala/tapasco/activity/Import.scala
View file @
7acd060d
...
...
@@ -129,7 +129,7 @@ object Import {
private
def
evaluateCore
(
c
:
Core
,
t
:
Target
,
optimization
:
Int
,
synthOptions
:
Option
[
String
]
=
None
)
(
implicit
cfg
:
Configuration
)
:
Boolean
=
{
logger
.
trace
(
"looking for SynthesisReport ..."
)
val
period
=
0.5
val
period
=
1.0
val
report
=
cfg
.
outputDir
(
c
,
t
).
resolve
(
"ipcore"
).
resolve
(
"%s_export.xml"
.
format
(
c
.
name
))
FileAssetManager
.
reports
.
synthReport
(
c
.
name
,
t
)
map
{
hls_report
=>
logger
.
trace
(
"found existing synthesis report: "
+
hls_report
)
...
...
Jens Korinth
@jk
mentioned in commit
786777b1
·
Feb 23, 2018
mentioned in commit
786777b1
mentioned in commit 786777b12cd7d84cb7b8fba48a52dd5d8f322840
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