Commit 7ef8a06c authored by Jaco Hofmann's avatar Jaco Hofmann
Browse files

Add frequencies for NetFPGA SUME clocks

parent 7c83a63b
......@@ -36,11 +36,13 @@ namespace eval platform {
CONFIG.MIG_DONT_TOUCH_PARAM {Custom} \
CONFIG.BOARD_MIG_PARAM {Custom}] $mig_7series_0
set clk_ref_i [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 clk_ref ]
connect_bd_intf_net $clk_ref_i [get_bd_intf_pins $name/CLK_REF]
set sys_clk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk ]
connect_bd_intf_net $sys_clk [get_bd_intf_pins $name/SYS_CLK]
set_property CONFIG.FREQ_HZ 233333333 $sys_clk
set clk_ref_i [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 clk_ref ]
connect_bd_intf_net $clk_ref_i [get_bd_intf_pins $name/CLK_REF]
set_property CONFIG.FREQ_HZ 200000000 $clk_ref_i
make_bd_pins_external [get_bd_pins $name/sys_rst]
......
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