Move all IP block related code into new namespace ip

* tapasco::ip contains methods to instantiate common IP
* common/ip.tcl automatically generates methods based on the stdcomps
  directory: every name has its own instantiation method called
  create_<name>, which takes only a name as an argument
* specialized constructors go into common_ip.tcl and can override the
  auto-generated ones
* removed all createXY procs in common.tcl and fixed all dependent
  scripts accordingly
* removed ill-fated "clocks_and_resets" bundle - sad, but didn't work
  correctly in Vivado

arch/axi4mm/axi4mm.tcl

@@ -16,9 +16,9 @@
 # You should have received a copy of the GNU Lesser General Public License
 # along with Tapasco.  If not, see <http://www.gnu.org/licenses/>.
 #
-# @file		axi4mm.tcl
-# @brief	AXI4 memory mapped master/slave interface based Architectures.
-# @author	J. Korinth, TU Darmstadt (jk@esa.tu-darmstadt.de)
+# @file    axi4mm.tcl
+# @brief  AXI4 memory mapped master/slave interface based Architectures.
+# @author  J. Korinth, TU Darmstadt (jk@esa.tu-darmstadt.de)
 #
 namespace eval arch {
   namespace export create
@@ -318,7 +318,7 @@ namespace eval arch {
     set i 0
     set j 0
     set left [llength $ips]
-    set cc [tapasco::createConcat "xlconcat_$j" [expr "[llength $ips] > 32 ? 32 : [llength $ips]"]]
+    set cc [tapasco::ip::create_xlconcat "xlconcat_$j" [expr "[llength $ips] > 32 ? 32 : [llength $ips]"]]
     lappend arch_irq_concats $cc
     foreach ip [lsort $ips] {
       foreach pin [get_bd_pins -of $ip -filter { TYPE == intr }] {
@@ -327,11 +327,11 @@ namespace eval arch {
         incr left -1
         if {$i > 31} {
           set i 0
-  	incr j
-  	if { $left > 0 } {
-  	  set cc [tapasco::createConcat "xlconcat_$j" [expr "$left > 32 ? 32 : $left"]]
-  	  lappend arch_irq_concats $cc
-  	}
+          incr j
+          if { $left > 0 } {
+            set cc [tapasco::ip::create_xlconcat "xlconcat_$j" [expr "$left > 32 ? 32 : $left"]]
+            lappend arch_irq_concats $cc
+          }
         }
       }
     }

arch/axi4mm/plugins/debug.tcl

@@ -36,7 +36,7 @@ namespace eval debug {
           set i 0
           foreach ifs $interfaces {
             if {[llength $ifs] == 3} {
-              set s_ila [tapasco::createSystemILA "SILA_$i" $num_ifs $depth $stages]
+              set s_ila [tapasco::create_system_ila "SILA_$i" $num_ifs $depth $stages]
               puts "  ifs = $ifs"
               set intf [get_bd_intf_pins [lindex $ifs 0]]
               set clk [get_bd_pins [lindex $ifs 1]]

arch/axi4mm/plugins/full_axi_slave_wrapper.tcl

@@ -45,7 +45,7 @@ namespace eval full_axi_wrapper {
       foreach fs $full_slave_ifs {
         # create slave port
         set saxi_port [create_bd_intf_pin -vlnv "xilinx.com:interface:aximm_rtl:1.0" -mode Slave "S_AXI_LITE_$si"]
-        set conv [tapasco::createProtocolConverter "conv_$si" "AXI4LITE" [get_property CONFIG.PROTOCOL $fs]]
+        set conv [tapasco::ip::create_proto_conv "conv_$si" "AXI4LITE" [get_property CONFIG.PROTOCOL $fs]]
         connect_bd_intf_net $saxi_port [get_bd_intf_pins -of_objects $conv -filter {MODE == Slave}]
         connect_bd_intf_net [get_bd_intf_pins -filter {MODE == Master} -of_objects $conv] $fs
         incr si

common/common_2016.4.tcl

 # create a dictionary of compatible VLNVs
 source $::env(TAPASCO_HOME)/common/common_ip.tcl
-dict set stdcomps axi_ic vlnv "xilinx.com:ip:axi_interconnect:2.1"
-dict set stdcomps ps vlnv "xilinx.com:ip:processing_system7:5.5"
-dict set stdcomps ps_bfm vlnv "xilinx.com:ip:processing_system7_bfm:2.0"
-dict set stdcomps axi_irqc vlnv "xilinx.com:ip:axi_intc:4.1"
-dict set stdcomps axi_cache vlnv "xilinx.com:ip:system_cache:3.0"
-dict set stdcomps xlconcat vlnv "xilinx.com:ip:xlconcat:2.1"
-dict set stdcomps xlslice vlnv "xilinx.com:ip:xlslice:1.0"
-dict set stdcomps xlconst vlnv "xilinx.com:ip:xlconstant:1.1"
-dict set stdcomps rst_gen vlnv "xilinx.com:ip:proc_sys_reset:5.0"
-dict set stdcomps proto_conv vlnv "xilinx.com:ip:axi_protocol_converter:2.1"
-dict set stdcomps bincnt vlnv "xilinx.com:ip:c_counter_binary:12.0"
 dict set stdcomps dualdma vlnv "esa.informatik.tu-darmstadt.de:user:dual_dma:1.7"
-dict set stdcomps oled_ctrl vlnv "esa.cs.tu-darmstadt.de:user:oled_pc:1.0"
-dict set stdcomps mm_to_lite vlnv "esa.cs.tu-darmstadt.de:user:mm_to_lite:1.0"
-dict set stdcomps system_cache vlnv "xilinx.com:ip:system_cache:3.1"
-dict set stdcomps mig_core vlnv "xilinx.com:ip:mig_7series:4.0"
-dict set stdcomps axi_pcie3_0 vlnv "xilinx.com:ip:axi_pcie3:3.0"
-dict set stdcomps tapasco_status vlnv "esa.cs.tu-darmstadt.de:tapasco:tapasco_status:1.2"
-dict set stdcomps clk_wiz "xilinx.com:ip:clk_wiz:5.3"
-dict set stdcomps msix_intr_ctrl vlnv "esa.informatik.tu-darmstadt.de:user:MSIXIntrCtrl:1.0"
-dict set stdcomps axi_reg_slice vlnv "xilinx.com:ip:axi_register_slice:2.1"
-dict set stdcomps dwidth_conv vlnv "xilinx.com:ip:axi_dwidth_converter:2.1"
-dict set stdcomps system_ila vlnv "xilinx.com:ip:system_ila:1.0"
+dict set stdcomps clk_wiz vlnv "xilinx.com:ip:clk_wiz:5.3"

common/common_2017.1.tcl

 # create a dictionary of compatible VLNVs
 source $::env(TAPASCO_HOME)/common/common_ip.tcl
-dict set stdcomps axi_ic vlnv "xilinx.com:ip:axi_interconnect:2.1"
-dict set stdcomps ps vlnv "xilinx.com:ip:processing_system7:5.5"
-dict set stdcomps ps_bfm vlnv "xilinx.com:ip:processing_system7_bfm:2.0"
-dict set stdcomps axi_irqc vlnv "xilinx.com:ip:axi_intc:4.1"
-dict set stdcomps axi_cache vlnv "xilinx.com:ip:system_cache:3.0"
-dict set stdcomps xlconcat vlnv "xilinx.com:ip:xlconcat:2.1"
-dict set stdcomps xlslice vlnv "xilinx.com:ip:xlslice:1.0"
-dict set stdcomps xlconst vlnv "xilinx.com:ip:xlconstant:1.1"
-dict set stdcomps rst_gen vlnv "xilinx.com:ip:proc_sys_reset:5.0"
-dict set stdcomps proto_conv vlnv "xilinx.com:ip:axi_protocol_converter:2.1"
-dict set stdcomps bincnt vlnv "xilinx.com:ip:c_counter_binary:12.0"
 dict set stdcomps dualdma vlnv "esa.informatik.tu-darmstadt.de:user:dual_dma:1.8"
-dict set stdcomps oled_ctrl vlnv "esa.cs.tu-darmstadt.de:user:oled_pc:1.0"
-dict set stdcomps mm_to_lite vlnv "esa.cs.tu-darmstadt.de:user:mm_to_lite:1.0"
-dict set stdcomps system_cache vlnv "xilinx.com:ip:system_cache:3.1"
-dict set stdcomps mig_core vlnv "xilinx.com:ip:mig_7series:4.0"
-dict set stdcomps axi_pcie3_0 vlnv "xilinx.com:ip:axi_pcie3:3.0"
-dict set stdcomps tapasco_status vlnv "esa.cs.tu-darmstadt.de:tapasco:tapasco_status:1.2"
-dict set stdcomps clk_wiz "xilinx.com:ip:clk_wiz:5.4"
-dict set stdcomps msix_intr_ctrl vlnv "esa.informatik.tu-darmstadt.de:user:MSIXIntrCtrl:1.0"
-dict set stdcomps axi_reg_slice vlnv "xilinx.com:ip:axi_register_slice:2.1"
-dict set stdcomps dwidth_conv vlnv "xilinx.com:ip:axi_dwidth_converter:2.1"
-dict set stdcomps system_ila vlnv "xilinx.com:ip:system_ila:1.0"

common/common_2017.2.tcl

 # create a dictionary of compatible VLNVs
 source $::env(TAPASCO_HOME)/common/common_ip.tcl
-dict set stdcomps axi_ic vlnv "xilinx.com:ip:axi_interconnect:2.1"
-dict set stdcomps ps vlnv "xilinx.com:ip:processing_system7:5.5"
-dict set stdcomps ps_bfm vlnv "xilinx.com:ip:processing_system7_bfm:2.0"
-dict set stdcomps axi_irqc vlnv "xilinx.com:ip:axi_intc:4.1"
-dict set stdcomps axi_cache vlnv "xilinx.com:ip:system_cache:3.0"
-dict set stdcomps xlconcat vlnv "xilinx.com:ip:xlconcat:2.1"
-dict set stdcomps xlslice vlnv "xilinx.com:ip:xlslice:1.0"
-dict set stdcomps xlconst vlnv "xilinx.com:ip:xlconstant:1.1"
-dict set stdcomps rst_gen vlnv "xilinx.com:ip:proc_sys_reset:5.0"
-dict set stdcomps proto_conv vlnv "xilinx.com:ip:axi_protocol_converter:2.1"
-dict set stdcomps bincnt vlnv "xilinx.com:ip:c_counter_binary:12.0"
-dict set stdcomps dualdma vlnv "esa.informatik.tu-darmstadt.de:user:dual_dma:1.9"
-dict set stdcomps oled_ctrl vlnv "esa.cs.tu-darmstadt.de:user:oled_pc:1.0"
-dict set stdcomps mm_to_lite vlnv "esa.cs.tu-darmstadt.de:user:mm_to_lite:1.0"
-dict set stdcomps system_cache vlnv "xilinx.com:ip:system_cache:3.1"
-dict set stdcomps mig_core vlnv "xilinx.com:ip:mig_7series:4.0"
-dict set stdcomps axi_pcie3_0 vlnv "xilinx.com:ip:axi_pcie3:3.0"
-dict set stdcomps tapasco_status vlnv "esa.cs.tu-darmstadt.de:tapasco:tapasco_status:1.2"
-dict set stdcomps clk_wiz "xilinx.com:ip:clk_wiz:5.4"
-dict set stdcomps msix_intr_ctrl vlnv "esa.informatik.tu-darmstadt.de:user:MSIXIntrCtrl:1.0"
-dict set stdcomps axi_reg_slice vlnv "xilinx.com:ip:axi_register_slice:2.1"
-dict set stdcomps dwidth_conv vlnv "xilinx.com:ip:axi_dwidth_converter:2.1"
-dict set stdcomps system_ila vlnv "xilinx.com:ip:system_ila:1.0"

common/common_ip.tcl

 # create a dictionary of compatible VLNVs
-dict set stdcomps axi_ic vlnv "xilinx.com:ip:axi_interconnect:2.1"
-dict set stdcomps ps vlnv "xilinx.com:ip:processing_system7:5.5"
-dict set stdcomps ps_bfm vlnv "xilinx.com:ip:processing_system7_bfm:2.0"
-dict set stdcomps axi_irqc vlnv "xilinx.com:ip:axi_intc:4.1"
-dict set stdcomps axi_cache vlnv "xilinx.com:ip:system_cache:3.0"
-dict set stdcomps xlconcat vlnv "xilinx.com:ip:xlconcat:2.1"
-dict set stdcomps xlslice vlnv "xilinx.com:ip:xlslice:1.0"
-dict set stdcomps xlconst vlnv "xilinx.com:ip:xlconstant:1.1"
-dict set stdcomps rst_gen vlnv "xilinx.com:ip:proc_sys_reset:5.0"
-dict set stdcomps proto_conv vlnv "xilinx.com:ip:axi_protocol_converter:2.1"
-dict set stdcomps bincnt vlnv "xilinx.com:ip:c_counter_binary:12.0"
-dict set stdcomps dualdma vlnv "esa.informatik.tu-darmstadt.de:user:dual_dma:1.9"
-dict set stdcomps oled_ctrl vlnv "esa.cs.tu-darmstadt.de:user:oled_pc:1.0"
-dict set stdcomps mm_to_lite vlnv "esa.cs.tu-darmstadt.de:user:mm_to_lite:1.0"
-dict set stdcomps system_cache vlnv "xilinx.com:ip:system_cache:3.1"
-dict set stdcomps mig_core vlnv "xilinx.com:ip:mig_7series:4.0"
-dict set stdcomps axi_pcie3_0 vlnv "xilinx.com:ip:axi_pcie3:3.0"
-dict set stdcomps tapasco_status vlnv "esa.cs.tu-darmstadt.de:tapasco:tapasco_status:1.2"
-dict set stdcomps clk_wiz "xilinx.com:ip:clk_wiz:5.4"
-dict set stdcomps msix_intr_ctrl vlnv "esa.informatik.tu-darmstadt.de:user:MSIXIntrCtrl:1.0"
-dict set stdcomps axi_reg_slice vlnv "xilinx.com:ip:axi_register_slice:2.1"
-dict set stdcomps dwidth_conv vlnv "xilinx.com:ip:axi_dwidth_converter:2.1"
-dict set stdcomps system_ila vlnv "xilinx.com:ip:system_ila:1.0"
-dict set stdcomps aximm_intf vlnv "xilinx.com:interface:aximm_rtl:1.0"
-dict set stdcomps tapasco_clocks_resets vlnv "esa.cs.tu-darmstadt.de:tapasco:tapasco_clocks_resets_rtl:1.0"
-dict set stdcomps clocks_resets_m vlnv "esa.cs.tu-darmstadt.de:tapasco:clocks_resets_master_bridge:1.0"
-dict set stdcomps clocks_resets_s vlnv "esa.cs.tu-darmstadt.de:tapasco:clocks_resets_slave_bridge:1.0"
+dict set stdcomps   axi_ic           vlnv   "xilinx.com:ip:axi_interconnect:2.1"
+dict set stdcomps   ps               vlnv   "xilinx.com:ip:processing_system7:5.5"
+dict set stdcomps   ps_bfm           vlnv   "xilinx.com:ip:processing_system7_bfm:2.0"
+dict set stdcomps   axi_irqc         vlnv   "xilinx.com:ip:axi_intc:4.1"
+dict set stdcomps   axi_cache        vlnv   "xilinx.com:ip:system_cache:3.0"
+dict set stdcomps   xlconcat         vlnv   "xilinx.com:ip:xlconcat:2.1"
+dict set stdcomps   xlslice          vlnv   "xilinx.com:ip:xlslice:1.0"
+dict set stdcomps   xlconst          vlnv   "xilinx.com:ip:xlconstant:1.1"
+dict set stdcomps   rst_gen          vlnv   "xilinx.com:ip:proc_sys_reset:5.0"
+dict set stdcomps   proto_conv       vlnv   "xilinx.com:ip:axi_protocol_converter:2.1"
+dict set stdcomps   bincnt           vlnv   "xilinx.com:ip:c_counter_binary:12.0"
+dict set stdcomps   dualdma          vlnv   "esa.informatik.tu-darmstadt.de:user:dual_dma:1.9"
+dict set stdcomps   oled_ctrl        vlnv   "esa.cs.tu-darmstadt.de:user:oled_pc:1.0"
+dict set stdcomps   mm_to_lite       vlnv   "esa.cs.tu-darmstadt.de:user:mm_to_lite:1.0"
+dict set stdcomps   system_cache     vlnv   "xilinx.com:ip:system_cache:3.1"
+dict set stdcomps   mig_core         vlnv   "xilinx.com:ip:mig_7series:4.0"
+dict set stdcomps   axi_pcie3_0      vlnv   "xilinx.com:ip:axi_pcie3:3.0"
+dict set stdcomps   tapasco_status   vlnv   "esa.cs.tu-darmstadt.de:tapasco:tapasco_status:1.2"
+dict set stdcomps   clk_wiz          vlnv   "xilinx.com:ip:clk_wiz:5.4"
+dict set stdcomps   msix_intr_ctrl   vlnv   "esa.informatik.tu-darmstadt.de:user:MSIXIntrCtrl:1.0"
+dict set stdcomps   axi_reg_slice    vlnv   "xilinx.com:ip:axi_register_slice:2.1"
+dict set stdcomps   dwidth_conv      vlnv   "xilinx.com:ip:axi_dwidth_converter:2.1"
+dict set stdcomps   system_ila       vlnv   "xilinx.com:ip:system_ila:1.0"
+dict set stdcomps   aximm_intf       vlnv   "xilinx.com:interface:aximm_rtl:1.0"

common/interfaces/tapasco_clocks_resets/master_bridge/master_bridge.v

-module ClockResetsMasterBridge(
-	input i_host_clk,
-	input i_host_peripheral_resetn,
-	input i_host_peripheral_reset,
-	input i_host_interconnect_resetn,
-	input i_design_clk,
-	input i_design_peripheral_resetn,
-	input i_design_peripheral_reset,
-	input i_design_interconnect_resetn,
-	input i_mem_clk,
-	input i_mem_peripheral_resetn,
-	input i_mem_peripheral_reset,
-	input i_mem_interconnect_resetn,
-	output o_host_clk,
-	output o_host_peripheral_resetn,
-	output o_host_peripheral_reset,
-	output o_host_interconnect_resetn,
-	output o_design_clk,
-	output o_design_peripheral_resetn,
-	output o_design_peripheral_reset,
-	output o_design_interconnect_resetn,
-	output o_mem_clk,
-	output o_mem_peripheral_resetn,
-	output o_mem_peripheral_reset,
-	output o_mem_interconnect_resetn
-);
-
-	assign o_host_clk = i_host_clk;
-	assign o_host_peripheral_resetn = i_host_peripheral_resetn;
-	assign o_host_peripheral_reset = i_host_peripheral_reset;
-	assign o_host_interconnect_resetn = i_host_interconnect_resetn;
-	assign o_design_clk = i_design_clk;
-	assign o_design_peripheral_resetn = i_design_peripheral_resetn;
-	assign o_design_peripheral_reset = i_design_peripheral_reset;
-	assign o_design_interconnect_resetn = i_design_interconnect_resetn;
-	assign o_mem_clk = i_mem_clk;
-	assign o_mem_peripheral_resetn = i_mem_peripheral_resetn;
-	assign o_mem_peripheral_reset = i_mem_peripheral_reset;
-	assign o_mem_interconnect_resetn = i_mem_interconnect_resetn;
-	
-endmodule

common/interfaces/tapasco_clocks_resets/master_bridge/xgui/ClockResetsMasterBridge_v1_0.tcl

-# Definitional proc to organize widgets for parameters.
-proc init_gui { IPINST } {
-  ipgui::add_param $IPINST -name "Component_Name"
-  #Adding Page
-  ipgui::add_page $IPINST -name "Page 0"
-
-
-}
-
-

common/interfaces/tapasco_clocks_resets/master_bridge/xgui/clocks_resets_master_bridge_v1_0.tcl

-# Definitional proc to organize widgets for parameters.
-proc init_gui { IPINST } {
-  ipgui::add_param $IPINST -name "Component_Name"
-  #Adding Page
-  ipgui::add_page $IPINST -name "Page 0"
-
-
-}
-
-

common/interfaces/tapasco_clocks_resets/slave_bridge/slave_bridge.v

-module ClockResetsSlaveBridge(
-	input i_host_clk,
-	input i_host_peripheral_resetn,
-	input i_host_peripheral_reset,
-	input i_host_interconnect_resetn,
-	input i_design_clk,
-	input i_design_peripheral_resetn,
-	input i_design_peripheral_reset,
-	input i_design_interconnect_resetn,
-	input i_mem_clk,
-	input i_mem_peripheral_resetn,
-	input i_mem_peripheral_reset,
-	input i_mem_interconnect_resetn,
-	output o_host_clk,
-	output o_host_peripheral_resetn,
-	output o_host_peripheral_reset,
-	output o_host_interconnect_resetn,
-	output o_design_clk,
-	output o_design_peripheral_resetn,
-	output o_design_peripheral_reset,
-	output o_design_interconnect_resetn,
-	output o_mem_clk,
-	output o_mem_peripheral_resetn,
-	output o_mem_peripheral_reset,
-	output o_mem_interconnect_resetn
-);
-
-	assign o_host_clk = i_host_clk;
-	assign o_host_peripheral_resetn = i_host_peripheral_resetn;
-	assign o_host_peripheral_reset = i_host_peripheral_reset;
-	assign o_host_interconnect_resetn = i_host_interconnect_resetn;
-	assign o_design_clk = i_design_clk;
-	assign o_design_peripheral_resetn = i_design_peripheral_resetn;
-	assign o_design_peripheral_reset = i_design_peripheral_reset;
-	assign o_design_interconnect_resetn = i_design_interconnect_resetn;
-	assign o_mem_clk = i_mem_clk;
-	assign o_mem_peripheral_resetn = i_mem_peripheral_resetn;
-	assign o_mem_peripheral_reset = i_mem_peripheral_reset;
-	assign o_mem_interconnect_resetn = i_mem_interconnect_resetn;
-	
-endmodule

common/interfaces/tapasco_clocks_resets/slave_bridge/xgui/ClockResetsSlaveBridge_v1_0.tcl

-# Definitional proc to organize widgets for parameters.
-proc init_gui { IPINST } {
-  ipgui::add_param $IPINST -name "Component_Name"
-  #Adding Page
-  ipgui::add_page $IPINST -name "Page 0"
-
-
-}
-
-

common/interfaces/tapasco_clocks_resets/slave_bridge/xgui/clocks_resets_slave_bridge_v1_0.tcl

-# Definitional proc to organize widgets for parameters.
-proc init_gui { IPINST } {
-  ipgui::add_param $IPINST -name "Component_Name"
-  #Adding Page
-  ipgui::add_page $IPINST -name "Page 0"
-
-
-}
-
-

common/interfaces/tapasco_clocks_resets/tapasco_clocks_resets.xml

-<?xml version="1.0" encoding="UTF-8"?>
-<spirit:busDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
-  <spirit:vendor>esa.cs.tu-darmstadt.de</spirit:vendor>
-  <spirit:library>tapasco</spirit:library>
-  <spirit:name>tapasco_clocks_resets</spirit:name>
-  <spirit:version>1.0</spirit:version>
-  <spirit:directConnection>true</spirit:directConnection>
-  <spirit:isAddressable>false</spirit:isAddressable>
-  <spirit:maxMasters>1</spirit:maxMasters>
-  <spirit:description>Clock and reset ports of the three core clock systems: Host, Design and Memory.</spirit:description>
-</spirit:busDefinition>

common/interfaces/tapasco_clocks_resets/tapasco_clocks_resets_rtl.xml

-<?xml version="1.0" encoding="UTF-8"?>
-<spirit:abstractionDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
-  <spirit:vendor>esa.cs.tu-darmstadt.de</spirit:vendor>
-  <spirit:library>tapasco</spirit:library>
-  <spirit:name>tapasco_clocks_resets_rtl</spirit:name>
-  <spirit:version>1.0</spirit:version>
-  <spirit:busType spirit:vendor="esa.cs.tu-darmstadt.de" spirit:library="tapasco" spirit:name="tapasco_clocks_resets" spirit:version="1.0"/>
-  <spirit:ports>
-    <spirit:port>
-      <spirit:logicalName>design_clk</spirit:logicalName>
-      <spirit:description>Design clock (i.e., Architecture base clock).</spirit:description>
-      <spirit:wire>
-        <spirit:qualifier>
-          <spirit:isClock>true</spirit:isClock>
-        </spirit:qualifier>
-        <spirit:onMaster>
-          <spirit:width>1</spirit:width>
-        </spirit:onMaster>
-        <spirit:onSlave>
-          <spirit:width>1</spirit:width>
-          <spirit:direction>in</spirit:direction>
-        </spirit:onSlave>
-      </spirit:wire>
-    </spirit:port>
-    <spirit:port>
-      <spirit:logicalName>design_peripheral_resetn</spirit:logicalName>
-      <spirit:description>Peripheral active-low reset synced to design clock.</spirit:description>
-      <spirit:wire>
-        <spirit:qualifier>
-          <spirit:isReset>true</spirit:isReset>
-        </spirit:qualifier>
-        <spirit:onMaster>
-          <spirit:width>1</spirit:width>
-        </spirit:onMaster>
-        <spirit:onSlave>
-          <spirit:width>1</spirit:width>
-          <spirit:direction>in</spirit:direction>
-        </spirit:onSlave>
-      </spirit:wire>
-    </spirit:port>
-    <spirit:port>
-      <spirit:logicalName>design_peripheral_reset</spirit:logicalName>
-      <spirit:description>Peripheral active-high reset synced to design clock.</spirit:description>
-      <spirit:wire>
-        <spirit:qualifier>
-          <spirit:isReset>true</spirit:isReset>
-        </spirit:qualifier>
-        <spirit:onMaster>
-          <spirit:width>1</spirit:width>
-        </spirit:onMaster>
-        <spirit:onSlave>
-          <spirit:presence>required</spirit:presence>
-          <spirit:width>1</spirit:width>
-          <spirit:direction>in</spirit:direction>
-        </spirit:onSlave>
-      </spirit:wire>
-    </spirit:port>
-    <spirit:port>
-      <spirit:logicalName>design_interconnect_resetn</spirit:logicalName>
-      <spirit:description>Interconnect active-low reset synced to design clock.</spirit:description>
-      <spirit:wire>
-        <spirit:qualifier>
-          <spirit:isReset>true</spirit:isReset>
-        </spirit:qualifier>
-        <spirit:onMaster>
-          <spirit:width>1</spirit:width>
-        </spirit:onMaster>
-        <spirit:onSlave>
-          <spirit:width>1</spirit:width>
-          <spirit:direction>in</spirit:direction>
-        </spirit:onSlave>
-      </spirit:wire>
-    </spirit:port>
-    <spirit:port>
-      <spirit:logicalName>host_clk</spirit:logicalName>
-      <spirit:description>Host clock (i.e., clock of host interfaces).</spirit:description>
-      <spirit:wire>
-        <spirit:qualifier>
-          <spirit:isClock>true</spirit:isClock>
-        </spirit:qualifier>
-        <spirit:onMaster>
-          <spirit:width>1</spirit:width>
-        </spirit:onMaster>
-        <spirit:onSlave>
-          <spirit:width>1</spirit:width>
-          <spirit:direction>in</spirit:direction>
-        </spirit:onSlave>
-      </spirit:wire>
-    </spirit:port>
-    <spirit:port>
-      <spirit:logicalName>host_peripheral_resetn</spirit:logicalName>
-      <spirit:description>Peripheral active-low reset synced to host clock.</spirit:description>
-      <spirit:wire>
-        <spirit:qualifier>
-          <spirit:isReset>true</spirit:isReset>
-        </spirit:qualifier>
-        <spirit:onMaster>
-          <spirit:width>1</spirit:width>
-        </spirit:onMaster>
-        <spirit:onSlave>
-          <spirit:width>1</spirit:width>
-          <spirit:direction>in</spirit:direction>
-        </spirit:onSlave>
-      </spirit:wire>
-    </spirit:port>
-    <spirit:port>
-      <spirit:logicalName>host_peripheral_reset</spirit:logicalName>
-      <spirit:description>Peripheral active-high reset synced to host clock.</spirit:description>
-      <spirit:wire>
-        <spirit:qualifier>
-          <spirit:isReset>true</spirit:isReset>
-        </spirit:qualifier>
-        <spirit:onMaster>
-          <spirit:width>1</spirit:width>
-        </spirit:onMaster>
-        <spirit:onSlave>
-          <spirit:width>1</spirit:width>
-          <spirit:direction>in</spirit:direction>
-        </spirit:onSlave>
-      </spirit:wire>
-    </spirit:port>
-    <spirit:port>
-      <spirit:logicalName>host_interconnect_resetn</spirit:logicalName>
-      <spirit:description>Interconnect active-low reset synced to host clock.</spirit:description>
-      <spirit:wire>
-        <spirit:qualifier>
-          <spirit:isReset>true</spirit:isReset>
-        </spirit:qualifier>
-        <spirit:onMaster>
-          <spirit:width>1</spirit:width>
-        </spirit:onMaster>
-        <spirit:onSlave>
-          <spirit:width>1</spirit:width>
-          <spirit:direction>in</spirit:direction>
-        </spirit:onSlave>
-      </spirit:wire>
-    </spirit:port>
-    <spirit:port>
-      <spirit:logicalName>mem_clk</spirit:logicalName>
-      <spirit:description>Memory clock (i.e., base clock for memory subsystem).</spirit:description>
-      <spirit:wire>
-        <spirit:qualifier>
-          <spirit:isClock>true</spirit:isClock>
-        </spirit:qualifier>
-        <spirit:onMaster>
-          <spirit:width>1</spirit:width>
-        </spirit:onMaster>
-        <spirit:onSlave>
-          <spirit:width>1</spirit:width>
-          <spirit:direction>in</spirit:direction>
-        </spirit:onSlave>
-      </spirit:wire>
-    </spirit:port>
-    <spirit:port>
-      <spirit:logicalName>mem_peripheral_resetn</spirit:logicalName>
-      <spirit:description>Peripheral active-low reset synced to mem clock.</spirit:description>
-      <spirit:wire>
-        <spirit:qualifier>
-          <spirit:isReset>true</spirit:isReset>
-        </spirit:qualifier>
-        <spirit:onMaster>
-          <spirit:width>1</spirit:width>
-        </spirit:onMaster>
-        <spirit:onSlave>
-          <spirit:width>1</spirit:width>
-          <spirit:direction>in</spirit:direction>
-        </spirit:onSlave>
-      </spirit:wire>
-    </spirit:port>
-    <spirit:port>
-      <spirit:logicalName>mem_peripheral_reset</spirit:logicalName>
-      <spirit:description>Peripheral active-high reset synced to mem clock.</spirit:description>
-      <spirit:wire>
-        <spirit:qualifier>
-          <spirit:isReset>true</spirit:isReset>
-        </spirit:qualifier>
-        <spirit:onMaster>
-          <spirit:width>1</spirit:width>
-        </spirit:onMaster>
-        <spirit:onSlave>
-          <spirit:width>1</spirit:width>
-          <spirit:direction>in</spirit:direction>
-        </spirit:onSlave>
-      </spirit:wire>
-    </spirit:port>
-    <spirit:port>
-      <spirit:logicalName>mem_interconnect_resetn</spirit:logicalName>
-      <spirit:description>Interconnect active-low reset synced to mem clock.</spirit:description>
-      <spirit:wire>
-        <spirit:qualifier>
-          <spirit:isReset>true</spirit:isReset>
-        </spirit:qualifier>
-        <spirit:onMaster>
-          <spirit:width>1</spirit:width>
-        </spirit:onMaster>
-        <spirit:onSlave>
-          <spirit:width>1</spirit:width>
-          <spirit:direction>in</spirit:direction>
-        </spirit:onSlave>
-      </spirit:wire>
-    </spirit:port>
-  </spirit:ports>
-</spirit:abstractionDefinition>

common/ip.tcl

+namespace eval ::tapasco::ip {
+  set stdcomps [dict create]
+
+  # check if we're running inside Vivado
+  if {[llength [info commands version]] > 0} {
+    # source IP catalog VLNVs for the current Vivado version
+    set cip [format "$::env(TAPASCO_HOME)/common/common_%s.tcl" [version -short]]
+    if {! [file exists $cip]} {
+      puts "Could not find $cip, Vivado [version -short] is not supported yet!"
+      exit 1
+    } {
+      source $cip
+    }
+  } {
+    puts "Skipping IP catalog."
+  }
+
+  # Automatically generate create proc for every known IP block.
+  # Can be overridden below.
+  foreach comp [dict keys $stdcomps] {
+    namespace export create_${comp}
+    set vlnv [dict get $stdcomps $comp "vlnv"]
+    proc create_${comp} {name} {
+      variable stdcomps
+      set comp_name [regsub {^([^:]*::)*create_} [lindex [info level 0] 0] {}]
+      set vlnv [dict get $stdcomps $comp_name "vlnv"]
+      puts "Creating component $name ..."
+      puts "  VLNV: $vlnv"
+      return [create_bd_cell -type ip -vlnv $vlnv $name]
+    }
+  }
+
+  namespace export get_vlnv
+
+  # Returns the VLNV for a given abstract TaPaSCo name.
+  proc get_vlnv {name} {
+    variable stdcomps
+    if {! [dict exists $stdcomps $name]} { error "VLNV for $name was not found in IP catalog!" }
+    return [dict get $stdcomps $name vlnv]
+  }
+
+  # Instantiates binary counter IP core.
+  # @param name Name of the instance.
+  # @param output_width Bit width of the counter.
+  # @return bd_cell of the instance.
+  proc create_bin_cnt {name width} {
+    variable stdcomps
+    puts "Creating $width-bits binary counter ..."
+    puts "  VLNV: [dict get $stdcomps bincnt vlnv]"
+
+    set bincnt [create_bd_cell -type ip -vlnv [dict get $stdcomps bincnt vlnv] $name]
+    # set bit-width
+    set_property -dict [list CONFIG.Output_Width $width CONFIG.Restrict_Count {false}] $bincnt
+    return $bincnt
+  }
+
+  # Instantiates an AXI4 Interrupt Controller IP core.
+  # @param name Name of the instance (default: axi_intc).
+  # @return bd_cell of the instance.
+  proc create_axi_irqc {{name axi_intc}} {
+    variable stdcomps