Commit 82ce7119 authored by Jens Korinth's avatar Jens Korinth
Browse files

Squashed 'common/ip/tapasco_status/' changes from e209f949..5b218b0

5b218b0 Pull chisel-axi
7cecbce Squashed 'axi/' changes from 01fad68..ec8f7a2
e56e93c Pull chisel-packaging
0e3cc98 Squashed 'packaging/' changes from c22243b..e6a5a78
4e421af Add assembly fatjar packaging, increase version to 1.0
41e37e7 Squashed 'axi/' changes from b8f4c554..01fad68
3fd53e7 Pull chisel-axi
872f551 Squashed 'packaging/' changes from 134b2f62..c22243b
88624e0 Pull chisel-packaging
f94b6de3 Remove caching of ivy repo from pipeline
43c331dc Pull chisel-axiutils
5937e2aa Implement cap0 bitfield
26d61dd6 Bugfix in pipeline
1030ffe5 Cache ivy2 repo in pipeline builds
14876b2e Implement support for capability field in Status Core
2a3e6856 Fix removed '<<=' sbt operator
bccc8a73 Run sbt test in GitLab pipeline
17e1a3a7 Fix bug concerning empty slots
5a089419 Ignore compiled python scripts in .gitignore
0f0a2d84 Update packaging to GitHub-version of Chisel3
a162cfae Update miscutils to GitHub-version of Chisel3
f0265156 Remove ununsed Scalactic dep
d146b992 Rename RegisterFile saxi port to s_axi

git-subtree-dir: common/ip/tapasco_status
git-subtree-split: 5b218b00f8f27f40c6cda836ddde5462f4296d33
parent e209f949
target/
project/
*.pyc
/chisel3/
/test/
# This file is a template, and might need editing before it works on your project.
# Official Java image. Look for the different tagged releases at
# https://hub.docker.com/r/library/java/tags/ . A Java image is not required
# but an image with a JVM speeds up the build a bit.
image: java:8
before_script:
# Enable the usage of sources over https
- apt-get update -yqq
- apt-get install apt-transport-https zip -yqq
# Add keyserver for SBT
- echo "deb http://dl.bintray.com/sbt/debian /" | tee -a /etc/apt/sources.list.d/sbt.list
- apt-key adv --keyserver hkp://keyserver.ubuntu.com:80 --recv 2EE0EA64E40A89B84B2DF73499E82A75642AC823
# Install SBT
- curl -s "https://get.sdkman.io" | bash
- source "/root/.sdkman/bin/sdkman-init.sh"
- sdk install sbt
# Log the sbt version and TaPaSCo version
- sbt sbtVersion version
test:
script:
# Execute your projects tests
- ./chiselSetup.sh
- sbt clean test
......@@ -7,4 +7,4 @@
/ip/
/packaging/target/
/miscutils/target/
*.pyc
......@@ -21,8 +21,7 @@ libraryDependencies ++= (Seq("chisel3","chisel-iotesters").map {
libraryDependencies ++= Seq(
"org.scalatest" %% "scalatest" % "3.0.4" % "test",
"org.scalacheck" %% "scalacheck" % "1.13.5" % "test",
"com.typesafe.play" %% "play-json" % "2.6.8",
"org.scalactic" %% "scalactic" % "3.0.4"
"com.typesafe.play" %% "play-json" % "2.6.8"
)
scalacOptions ++= Seq("-language:implicitConversions", "-language:reflectiveCalls", "-deprecation", "-feature")
......
package chisel.packaging
import chisel3._
import scala.sys.process._
import java.nio.file._
import scala.language.postfixOps
/** Module definition.
* @param config Optional, arbitrary configuration object, passed to post build actions.
......@@ -22,16 +24,35 @@ abstract class ModuleBuilder(packagingDir: String = "packaging") {
/** List of modules to build. */
val modules: Seq[ModuleDef]
private def extractScript(name: String): Path = {
val p = Paths.get(java.io.File.createTempFile("chisel-packaging-", "", null).getAbsolutePath.toString).resolveSibling(name)
val ps = new java.io.FileOutputStream(p.toFile)
val in = Option(getClass().getClassLoader().getResourceAsStream(name))
if (in.isEmpty) throw new Exception(s"$name not found in resources!")
in map { is =>
Iterator continually (is.read) takeWhile (-1 !=) foreach (ps.write)
ps.flush()
ps.close()
p.toFile.deleteOnExit()
p.toFile.setExecutable(true)
Paths.get(p.toString)
} get
}
def main(args: Array[String]) {
assert ((modules map (_.core.name.toLowerCase)).toSet.size == modules.length, "module names must be unique")
val fm = modules filter (m => args.length == 0 || args.map(_.toLowerCase).contains(m.core.name.toLowerCase))
assert (fm.length > 0, "no matching cores found for: " + args.mkString(", "))
val (packaging, axi) = (extractScript("package.py"), extractScript("axi4.py"))
System.err.println(s"packaging script in: ${packaging.toString}")
fm foreach { m =>
Driver.execute(chiselArgs ++ Array("--target-dir", m.core.root, "--top-name", m.core.name), m.constr)
m.core.postBuildActions map (fn => fn.apply(m.config))
val json = "%s/%s.json".format(m.core.root, m.core.name)
m.core.write(json)
"%s/package.py %s".format(packagingDir, json).!
s"${packaging.toString} %s".format(json).!
}
}
}
__port_map = {
'AWID' : 'io_{0}_writeAddr_bits_id',
'AWADDR' : 'io_{0}_writeAddr_bits_addr',
'AWLEN' : 'io_{0}_writeAddr_bits_burst_len',
'AWSIZE' : 'io_{0}_writeAddr_bits_burst_size',
'AWBURST' : 'io_{0}_writeAddr_bits_burst_burst',
'AWLOCK' : 'io_{0}_writeAddr_bits_lock_lock',
'AWCACHE' : 'io_{0}_writeAddr_bits_cache_cache',
'AWPROT' : 'io_{0}_writeAddr_bits_prot_prot',
'AWQOS' : 'io_{0}_writeAddr_bits_qos',
'AWREGION' : 'io_{0}_writeAddr_bits_region',
'AWUSER' : 'io_{0}_writeAddr_bits_user',
'AWVALID' : 'io_{0}_writeAddr_valid',
'AWREADY' : 'io_{0}_writeAddr_ready',
'WID' : 'io_{0}_writeData_bits_id',
'WDATA' : 'io_{0}_writeData_bits_data',
'WSTRB' : 'io_{0}_writeData_bits_strb_strb',
'WLAST' : 'io_{0}_writeData_bits_last',
'WUSER' : 'io_{0}_writeData_bits_user',
'WVALID' : 'io_{0}_writeData_valid',
'WREADY' : 'io_{0}_writeData_ready',
'BID' : 'io_{0}_writeResp_bits_bid',
'BRESP' : 'io_{0}_writeResp_bits_bresp',
'BUSER' : 'io_{0}_writeResp_bits_buser',
'BVALID' : 'io_{0}_writeResp_valid',
'BREADY' : 'io_{0}_writeResp_ready',
'ARID' : 'io_{0}_readAddr_bits_id',
'ARADDR' : 'io_{0}_readAddr_bits_addr',
'ARLEN' : 'io_{0}_readAddr_bits_burst_len',
'ARSIZE' : 'io_{0}_readAddr_bits_burst_size',
'ARBURST' : 'io_{0}_readAddr_bits_burst_burst',
'ARLOCK' : 'io_{0}_readAddr_bits_lock_lock',
'ARCACHE' : 'io_{0}_readAddr_bits_cache_cache',
'ARPROT' : 'io_{0}_readAddr_bits_prot_prot',
'ARQOS' : 'io_{0}_readAddr_bits_qos',
'ARREGION' : 'io_{0}_readAddr_bits_region',
'ARUSER' : 'io_{0}_readAddr_bits_user',
'ARVALID' : 'io_{0}_readAddr_valid',
'ARREADY' : 'io_{0}_readAddr_ready',
'RID' : 'io_{0}_readData_bits_id',
'RDATA' : 'io_{0}_readData_bits_data',
'RRESP' : 'io_{0}_readData_bits_resp',
'RLAST' : 'io_{0}_readData_bits_last',
'RUSER' : 'io_{0}_readData_bits_user',
'RVALID' : 'io_{0}_readData_valid',
'RREADY' : 'io_{0}_readData_ready'
'AWID' : 'io_{0}_writeAddr_bits_id',
'AWADDR' : 'io_{0}_writeAddr_bits_addr',
'AWLEN' : 'io_{0}_writeAddr_bits_burst_len',
'AWSIZE' : 'io_{0}_writeAddr_bits_burst_size',
'AWBURST' : 'io_{0}_writeAddr_bits_burst_burst',
'AWLOCK' : 'io_{0}_writeAddr_bits_lock_lock',
'AWCACHE' : 'io_{0}_writeAddr_bits_cache_cache',
'AWPROT' : 'io_{0}_writeAddr_bits_prot_prot',
'AWQOS' : 'io_{0}_writeAddr_bits_qos',
'AWREGION' : 'io_{0}_writeAddr_bits_region',
'AWUSER' : 'io_{0}_writeAddr_bits_user',
'AWVALID' : 'io_{0}_writeAddr_valid',
'AWREADY' : 'io_{0}_writeAddr_ready',
'WID' : 'io_{0}_writeData_bits_id',
'WDATA' : 'io_{0}_writeData_bits_data',
'WSTRB' : 'io_{0}_writeData_bits_strb_strb',
'WLAST' : 'io_{0}_writeData_bits_last',
'WUSER' : 'io_{0}_writeData_bits_user',
'WVALID' : 'io_{0}_writeData_valid',
'WREADY' : 'io_{0}_writeData_ready',
'BID' : 'io_{0}_writeResp_bits_bid',
'BRESP' : 'io_{0}_writeResp_bits_bresp',
'BUSER' : 'io_{0}_writeResp_bits_buser',
'BVALID' : 'io_{0}_writeResp_valid',
'BREADY' : 'io_{0}_writeResp_ready',
'ARID' : 'io_{0}_readAddr_bits_id',
'ARADDR' : 'io_{0}_readAddr_bits_addr',
'ARLEN' : 'io_{0}_readAddr_bits_burst_len',
'ARSIZE' : 'io_{0}_readAddr_bits_burst_size',
'ARBURST' : 'io_{0}_readAddr_bits_burst_burst',
'ARLOCK' : 'io_{0}_readAddr_bits_lock_lock',
'ARCACHE' : 'io_{0}_readAddr_bits_cache_cache',
'ARPROT' : 'io_{0}_readAddr_bits_prot_prot',
'ARQOS' : 'io_{0}_readAddr_bits_qos',
'ARREGION' : 'io_{0}_readAddr_bits_region',
'ARUSER' : 'io_{0}_readAddr_bits_user',
'ARVALID' : 'io_{0}_readAddr_valid',
'ARREADY' : 'io_{0}_readAddr_ready',
'RID' : 'io_{0}_readData_bits_id',
'RDATA' : 'io_{0}_readData_bits_data',
'RRESP' : 'io_{0}_readData_bits_resp',
'RLAST' : 'io_{0}_readData_bits_last',
'RUSER' : 'io_{0}_readData_bits_user',
'RVALID' : 'io_{0}_readData_valid',
'RREADY' : 'io_{0}_readData_ready'
}
def get_port_dict(name):
return {k: v.format(name) for k, v in __port_map.items()}
retdict = {}
for k, v in __port_map.items():
retdict[k] = v.format(name)
return retdict
......@@ -6,6 +6,11 @@ version := "0.3-SNAPSHOT"
scalaVersion := "2.11.11"
unmanagedResources in Compile ++= Seq(
baseDirectory.value / "package.py",
baseDirectory.value / "axi4.py"
)
resolvers ++= Seq(
Resolver.sonatypeRepo("snapshots"),
Resolver.sonatypeRepo("releases")
......
......@@ -55,7 +55,7 @@ object RegisterFile {
**/
class IO(cfg: Configuration)(implicit axi: Axi4Lite.Configuration) extends Bundle {
val addrWidth: AddrWidth = AddrWidth(Seq(cfg.minAddrWidth:Int, axi.addrWidth:Int).max)
val saxi = Axi4Lite.Slave(axi.copy(addrWidth = addrWidth))
val s_axi = Axi4Lite.Slave(axi.copy(addrWidth = addrWidth))
override def cloneType = new IO(cfg)(axi).asInstanceOf[this.type]
}
......@@ -63,49 +63,49 @@ object RegisterFile {
def behavior(cfg: RegisterFile.Configuration, io: RegisterFile.IO)
(implicit axi: Axi4Lite.Configuration, logger: Logging, logLevel: Logging.Level) {
class ReadData extends Bundle {
val data = io.saxi.readData.bits.data.cloneType
val resp = io.saxi.readData.bits.resp.cloneType
val data = io.s_axi.readData.bits.data.cloneType
val resp = io.s_axi.readData.bits.resp.cloneType
override def cloneType = (new ReadData).asInstanceOf[this.type]
}
val in_q_ra = Module(new Queue(io.saxi.readAddr.bits.addr.cloneType, entries = cfg.fifoDepth, pipe = true))
val in_q_wa = Module(new Queue(io.saxi.writeAddr.bits.addr.cloneType, entries = cfg.fifoDepth, pipe = true))
val in_q_wd = Module(new Queue(io.saxi.writeData.bits.data.cloneType, entries = cfg.fifoDepth, pipe = true))
val in_q_ra = Module(new Queue(io.s_axi.readAddr.bits.addr.cloneType, entries = cfg.fifoDepth, pipe = true))
val in_q_wa = Module(new Queue(io.s_axi.writeAddr.bits.addr.cloneType, entries = cfg.fifoDepth, pipe = true))
val in_q_wd = Module(new Queue(io.s_axi.writeData.bits.data.cloneType, entries = cfg.fifoDepth, pipe = true))
val read_reg = Reg((new ReadData).cloneType)
val resp_reg = RegNext(Response.slverr, init = Response.slverr)
val out_q_rd = Module(new Queue((new ReadData).cloneType, cfg.fifoDepth))
val out_q_wr = Module(new Queue(io.saxi.writeResp.bits.bresp.cloneType, cfg.fifoDepth))
io.saxi.readData.bits.defaults
io.saxi.readData.valid := false.B
io.saxi.writeResp.bits.defaults
io.saxi.writeResp.valid := false.B
in_q_ra.io.enq.bits := io.saxi.readAddr.bits.addr
in_q_ra.io.enq.valid := io.saxi.readAddr.valid
io.saxi.readAddr.ready := in_q_ra.io.enq.ready
in_q_wa.io.enq.bits := io.saxi.writeAddr.bits.addr
in_q_wa.io.enq.valid := io.saxi.writeAddr.valid
io.saxi.writeAddr.ready := in_q_wa.io.enq.ready
in_q_wd.io.enq.bits := io.saxi.writeData.bits.data
in_q_wd.io.enq.valid := io.saxi.writeData.valid
io.saxi.writeData.ready := in_q_wd.io.enq.ready
val out_q_wr = Module(new Queue(io.s_axi.writeResp.bits.bresp.cloneType, cfg.fifoDepth))
io.s_axi.readData.bits.defaults
io.s_axi.readData.valid := false.B
io.s_axi.writeResp.bits.defaults
io.s_axi.writeResp.valid := false.B
in_q_ra.io.enq.bits := io.s_axi.readAddr.bits.addr
in_q_ra.io.enq.valid := io.s_axi.readAddr.valid
io.s_axi.readAddr.ready := in_q_ra.io.enq.ready
in_q_wa.io.enq.bits := io.s_axi.writeAddr.bits.addr
in_q_wa.io.enq.valid := io.s_axi.writeAddr.valid
io.s_axi.writeAddr.ready := in_q_wa.io.enq.ready
in_q_wd.io.enq.bits := io.s_axi.writeData.bits.data
in_q_wd.io.enq.valid := io.s_axi.writeData.valid
io.s_axi.writeData.ready := in_q_wd.io.enq.ready
val out_q_rd_enq_valid = RegNext(false.B, init = false.B)
out_q_rd.io.enq.bits := read_reg
out_q_rd.io.enq.valid := out_q_rd_enq_valid
out_q_rd.io.deq.ready := io.saxi.readData.ready
io.saxi.readData.bits.data := out_q_rd.io.deq.bits.data
io.saxi.readData.bits.resp := out_q_rd.io.deq.bits.resp
io.saxi.readData.valid := out_q_rd.io.deq.valid
out_q_rd.io.deq.ready := io.s_axi.readData.ready
io.s_axi.readData.bits.data := out_q_rd.io.deq.bits.data
io.s_axi.readData.bits.resp := out_q_rd.io.deq.bits.resp
io.s_axi.readData.valid := out_q_rd.io.deq.valid
val out_q_wr_enq_valid = RegNext(false.B, init = false.B)
out_q_wr.io.enq.bits := resp_reg
out_q_wr.io.enq.valid := out_q_wr_enq_valid
out_q_wr.io.deq.ready := io.saxi.writeResp.ready
io.saxi.writeResp.valid := out_q_wr.io.deq.valid
io.saxi.writeResp.bits.bresp := out_q_wr.io.deq.bits
out_q_wr.io.deq.ready := io.s_axi.writeResp.ready
io.s_axi.writeResp.valid := out_q_wr.io.deq.valid
io.s_axi.writeResp.bits.bresp := out_q_wr.io.deq.bits
in_q_ra.io.deq.ready := out_q_rd.io.enq.ready
......@@ -141,11 +141,11 @@ object RegisterFile {
def resetBehavior(io: RegisterFile.IO)(implicit module: Module) {
when (module.reset.toBool) { // this is required for AXI compliance; apparently Queues start working while reset is high
io.saxi.readAddr.ready := false.B
io.saxi.readData.valid := false.B
io.saxi.writeAddr.ready := false.B
io.saxi.writeData.ready := false.B
io.saxi.writeResp.valid := false.B
io.s_axi.readAddr.ready := false.B
io.s_axi.readData.valid := false.B
io.s_axi.writeAddr.ready := false.B
io.s_axi.writeData.ready := false.B
io.s_axi.writeResp.valid := false.B
}
}
}
......
......@@ -26,7 +26,7 @@ class RegFileTest(val size: Int, val off: Int, regs: Map[Long, ControlRegister],
val saxi = Module(new RegisterFile(cfg))
val m = Module(new ProgrammableMaster(actions))
val io = IO(new Bundle {
val rdata = Irrevocable(saxi.io.saxi.readData.bits.cloneType)
val rdata = Irrevocable(saxi.io.s_axi.readData.bits.cloneType)
val wresp = Irrevocable(new chisel.axi.Axi4Lite.WriteResponse)
val finished = Output(Bool())
})
......@@ -34,10 +34,10 @@ class RegFileTest(val size: Int, val off: Int, regs: Map[Long, ControlRegister],
m.io.restart := 0.U
m.io.out.ready := true.B
m.io.w_resp.ready := true.B
m.io.maxi <> saxi.io.saxi
m.io.maxi <> saxi.io.s_axi
io.finished := m.io.finished
io.wresp <> saxi.io.saxi.writeResp
io.rdata <> saxi.io.saxi.readData
io.wresp <> saxi.io.s_axi.writeResp
io.rdata <> saxi.io.s_axi.readData
}
/** Unit test suite for Axi4LiteRegisterFile module. **/
......
......@@ -2,7 +2,7 @@ name := "tapasco-status"
organization := "esa.cs.tu-darmstadt.de"
version := "1.0-SNAPSHOT"
version := "1.0"
scalaVersion := "2.11.12"
......@@ -35,11 +35,6 @@ cleanFiles ++= Seq((baseDirectory.value / "test"), (baseDirectory.value / "ip"),
aggregate in test := false
lazy val chiselSetupTask = TaskKey[Unit]("chiselSetup", "Build latest chisel libs from source")
assemblyJarName in assembly := s"tapasco-status-${version.value}.jar"
chiselSetupTask := {
import sys.process._
"./chiselSetup.sh" !
}
compile in Compile <<= (compile in Compile).dependsOn(chiselSetupTask)
test in assembly := false
......@@ -28,5 +28,8 @@
}, {
"Domain" : "Memory",
"Frequency" : 200
} ]
}
\ No newline at end of file
} ],
"Capabilities" : {
"Capabilities 0" : 1
}
}
package chisel.packaging
import chisel3._
import scala.sys.process._
import java.nio.file._
import scala.language.postfixOps
/** Module definition.
* @param config Optional, arbitrary configuration object, passed to post build actions.
......@@ -22,16 +24,35 @@ abstract class ModuleBuilder(packagingDir: String = "packaging") {
/** List of modules to build. */
val modules: Seq[ModuleDef]
private def extractScript(name: String): Path = {
val p = Paths.get(java.io.File.createTempFile("chisel-packaging-", "", null).getAbsolutePath.toString).resolveSibling(name)
val ps = new java.io.FileOutputStream(p.toFile)
val in = Option(getClass().getClassLoader().getResourceAsStream(name))
if (in.isEmpty) throw new Exception(s"$name not found in resources!")
in map { is =>
Iterator continually (is.read) takeWhile (-1 !=) foreach (ps.write)
ps.flush()
ps.close()
p.toFile.deleteOnExit()
p.toFile.setExecutable(true)
Paths.get(p.toString)
} get
}
def main(args: Array[String]) {
assert ((modules map (_.core.name.toLowerCase)).toSet.size == modules.length, "module names must be unique")
val fm = modules filter (m => args.length == 0 || args.map(_.toLowerCase).contains(m.core.name.toLowerCase))
assert (fm.length > 0, "no matching cores found for: " + args.mkString(", "))
val (packaging, axi) = (extractScript("package.py"), extractScript("axi4.py"))
System.err.println(s"packaging script in: ${packaging.toString}")
fm foreach { m =>
Driver.execute(chiselArgs ++ Array("--target-dir", m.core.root, "--top-name", m.core.name), m.constr)
m.core.postBuildActions map (fn => fn.apply(m.config))
val json = "%s/%s.json".format(m.core.root, m.core.name)
m.core.write(json)
"%s/package.py %s".format(packagingDir, json).!
s"${packaging.toString} %s".format(json).!
}
}
}
__port_map = {
'AWID' : 'io_{0}_writeAddr_bits_id',
'AWADDR' : 'io_{0}_writeAddr_bits_addr',
'AWLEN' : 'io_{0}_writeAddr_bits_burst_len',
'AWSIZE' : 'io_{0}_writeAddr_bits_burst_size',
'AWBURST' : 'io_{0}_writeAddr_bits_burst_burst',
'AWLOCK' : 'io_{0}_writeAddr_bits_lock_lock',
'AWCACHE' : 'io_{0}_writeAddr_bits_cache_cache',
'AWPROT' : 'io_{0}_writeAddr_bits_prot_prot',
'AWQOS' : 'io_{0}_writeAddr_bits_qos',
'AWREGION' : 'io_{0}_writeAddr_bits_region',
'AWUSER' : 'io_{0}_writeAddr_bits_user',
'AWVALID' : 'io_{0}_writeAddr_valid',
'AWREADY' : 'io_{0}_writeAddr_ready',
'WID' : 'io_{0}_writeData_bits_id',
'WDATA' : 'io_{0}_writeData_bits_data',
'WSTRB' : 'io_{0}_writeData_bits_strb_strb',
'WLAST' : 'io_{0}_writeData_bits_last',
'WUSER' : 'io_{0}_writeData_bits_user',
'WVALID' : 'io_{0}_writeData_valid',
'WREADY' : 'io_{0}_writeData_ready',
'BID' : 'io_{0}_writeResp_bits_bid',
'BRESP' : 'io_{0}_writeResp_bits_bresp',
'BUSER' : 'io_{0}_writeResp_bits_buser',
'BVALID' : 'io_{0}_writeResp_valid',
'BREADY' : 'io_{0}_writeResp_ready',
'ARID' : 'io_{0}_readAddr_bits_id',
'ARADDR' : 'io_{0}_readAddr_bits_addr',
'ARLEN' : 'io_{0}_readAddr_bits_burst_len',
'ARSIZE' : 'io_{0}_readAddr_bits_burst_size',
'ARBURST' : 'io_{0}_readAddr_bits_burst_burst',
'ARLOCK' : 'io_{0}_readAddr_bits_lock_lock',
'ARCACHE' : 'io_{0}_readAddr_bits_cache_cache',
'ARPROT' : 'io_{0}_readAddr_bits_prot_prot',
'ARQOS' : 'io_{0}_readAddr_bits_qos',
'ARREGION' : 'io_{0}_readAddr_bits_region',
'ARUSER' : 'io_{0}_readAddr_bits_user',
'ARVALID' : 'io_{0}_readAddr_valid',
'ARREADY' : 'io_{0}_readAddr_ready',
'RID' : 'io_{0}_readData_bits_id',
'RDATA' : 'io_{0}_readData_bits_data',
'RRESP' : 'io_{0}_readData_bits_resp',
'RLAST' : 'io_{0}_readData_bits_last',
'RUSER' : 'io_{0}_readData_bits_user',
'RVALID' : 'io_{0}_readData_valid',
'RREADY' : 'io_{0}_readData_ready'
'AWID' : 'io_{0}_writeAddr_bits_id',
'AWADDR' : 'io_{0}_writeAddr_bits_addr',
'AWLEN' : 'io_{0}_writeAddr_bits_burst_len',
'AWSIZE' : 'io_{0}_writeAddr_bits_burst_size',
'AWBURST' : 'io_{0}_writeAddr_bits_burst_burst',
'AWLOCK' : 'io_{0}_writeAddr_bits_lock_lock',
'AWCACHE' : 'io_{0}_writeAddr_bits_cache_cache',
'AWPROT' : 'io_{0}_writeAddr_bits_prot_prot',
'AWQOS' : 'io_{0}_writeAddr_bits_qos',
'AWREGION' : 'io_{0}_writeAddr_bits_region',
'AWUSER' : 'io_{0}_writeAddr_bits_user',
'AWVALID' : 'io_{0}_writeAddr_valid',
'AWREADY' : 'io_{0}_writeAddr_ready',
'WID' : 'io_{0}_writeData_bits_id',
'WDATA' : 'io_{0}_writeData_bits_data',
'WSTRB' : 'io_{0}_writeData_bits_strb_strb',
'WLAST' : 'io_{0}_writeData_bits_last',
'WUSER' : 'io_{0}_writeData_bits_user',
'WVALID' : 'io_{0}_writeData_valid',
'WREADY' : 'io_{0}_writeData_ready',
'BID' : 'io_{0}_writeResp_bits_bid',
'BRESP' : 'io_{0}_writeResp_bits_bresp',
'BUSER' : 'io_{0}_writeResp_bits_buser',
'BVALID' : 'io_{0}_writeResp_valid',
'BREADY' : 'io_{0}_writeResp_ready',
'ARID' : 'io_{0}_readAddr_bits_id',
'ARADDR' : 'io_{0}_readAddr_bits_addr',
'ARLEN' : 'io_{0}_readAddr_bits_burst_len',
'ARSIZE' : 'io_{0}_readAddr_bits_burst_size',
'ARBURST' : 'io_{0}_readAddr_bits_burst_burst',
'ARLOCK' : 'io_{0}_readAddr_bits_lock_lock',
'ARCACHE' : 'io_{0}_readAddr_bits_cache_cache',
'ARPROT' : 'io_{0}_readAddr_bits_prot_prot',
'ARQOS' : 'io_{0}_readAddr_bits_qos',
'ARREGION' : 'io_{0}_readAddr_bits_region',
'ARUSER' : 'io_{0}_readAddr_bits_user',
'ARVALID' : 'io_{0}_readAddr_valid',
'ARREADY' : 'io_{0}_readAddr_ready',
'RID' : 'io_{0}_readData_bits_id',
'RDATA' : 'io_{0}_readData_bits_data',
'RRESP' : 'io_{0}_readData_bits_resp',
'RLAST' : 'io_{0}_readData_bits_last',
'RUSER' : 'io_{0}_readData_bits_user',
'RVALID' : 'io_{0}_readData_valid',
'RREADY' : 'io_{0}_readData_ready'
}
def get_port_dict(name):
return {k: v.format(name) for k, v in __port_map.items()}
retdict = {}
for k, v in __port_map.items():
retdict[k] = v.format(name)
return retdict
......@@ -6,6 +6,11 @@ version := "0.3-SNAPSHOT"
scalaVersion := "2.11.11"
unmanagedResources in Compile ++= Seq(
baseDirectory.value / "package.py",
baseDirectory.value / "axi4.py"
)
resolvers ++= Seq(
Resolver.sonatypeRepo("snapshots"),
Resolver.sonatypeRepo("releases")
......
addSbtPlugin("com.eed3si9n" % "sbt-assembly" % "0.14.6")
......@@ -14,67 +14,82 @@ object Builder {
implicit val axi: Axi4Lite.Configuration = Axi4Lite.Configuration(dataWidth = Axi4Lite.Width32,
addrWidth = AddrWidth(12))
private final val emptySlot = new ConstantRegister(Some("Empty Slot"), value = BigInt(0))
private def makeRegister(s: Slot): Seq[(Long, ControlRegister)] = s match {
case k: Slot.Kernel => Seq(
256L + s.slot * 16L -> new ConstantRegister(Some("Slot ${s.slot} Kernel ID"), value = BigInt(k.kernel)),
260L + s.slot * 16L -> new ConstantRegister(Some("Slot ${s.slot} Local Mem"), value = BigInt(0))
256L + s.slot * 16L -> new ConstantRegister(Some(s"Slot ${s.slot} Kernel ID"), value = BigInt(k.kernel)),
260L + s.slot * 16L -> new ConstantRegister(Some(s"Slot ${s.slot} Local Mem"), value = BigInt(0))
)
case m: Slot.Memory => Seq(
256L + s.slot * 16L -> new ConstantRegister(Some("Slot ${s.slot} Kernel ID"), value = BigInt(0)),
260L + s.slot * 16L -> new ConstantRegister(Some("Slot ${s.slot} Local Mem"), value = BigInt(m.size))
256L + s.slot * 16L -> new ConstantRegister(Some(s"Slot ${s.slot} Kernel ID"), value = BigInt(0)),
260L + s.slot * 16L -> new ConstantRegister(Some(s"Slot ${s.slot} Local Mem"), value = BigInt(m.size))
)
case k: Slot.Empty => Seq(
256L + s.slot * 16L -> emptySlot,
260L + s.slot * 16L -> emptySlot
)
}
private def fillEmptySlots(ss: Seq[Slot]): Seq[Slot] = {
val slotIds: Set[Int] = (ss map (_.slot: Int)).toSet
ss ++ (for (x <- 0 until NUM_SLOTS if !(slotIds.contains(x))) yield Slot.Empty(x))
}
def makeConfiguration(status: Status): RegisterFile.Configuration = RegisterFile.Configuration(
regs = (Seq[(Long, ControlRegister)](
0x00L -> new ConstantRegister(Some("Magic ID"), value = BigInt("E5AE1337", 16)),
0x04L -> new ConstantRegister(Some("Int Count"), value = BigInt(status.interruptControllers)),
0x08L -> new ConstantRegister(Some("Capabilities_0"), value = BigInt(0)), // FIXME CAPABILITIES_0
0x08L -> new ConstantRegister(Some("Capabilities_0"), value = BigInt(status.capabilities.cap0)),
0x10L -> new ConstantRegister(Some("Vivado Version"), value = BigInt(status.versions.vivado.toHex, 16)),
0x14L -> new ConstantRegister(Some("Vivado Version"), value = BigInt(status.versions.tapasco.toHex, 16)),
0x18L -> new ConstantRegister(Some("Bitstream Timestamp"), value = BigInt(status.timestamp)),
0x1CL -> new ConstantRegister(Some("Host Clock (Hz)"), value = BigInt(status.clocks.host.frequency.toLong)),
0x20L -> new ConstantRegister(Some("Design Clock (Hz)"), value = BigInt(status.clocks.design.frequency.toLong)),
0x24L -> new ConstantRegister(Some("Memory Clock (Hz)"), value = BigInt(status.clocks.memory.frequency.toLong))
) ++ ((status.config map (makeRegister _) fold Seq