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tapasco
tapasco
Commits
82e7d31a
Commit
82e7d31a
authored
Aug 26, 2017
by
Jens Korinth
Browse files
Merged chisel-miscutils
Merge commit 'fe9856d869b808e52fc1a27225f684c78b392230'
parents
03be2246
ce2a5d30
Changes
7
Hide whitespace changes
Inline
Side-by-side
miscutils/build.sbt
View file @
82e7d31a
...
...
@@ -2,7 +2,7 @@ name := "chisel-miscutils"
organization
:=
"esa.cs.tu-darmstadt.de"
version
:=
"0.
3
-SNAPSHOT"
version
:=
"0.
4
-SNAPSHOT"
scalaVersion
:=
"2.11.11"
...
...
miscutils/src/main/scala/DecoupledDataSource.scala
View file @
82e7d31a
...
...
@@ -20,10 +20,14 @@ class DecoupledDataSourceIO[T <: Data](gen: T) extends Bundle {
otherwise valid will go low after data was
consumed.
**/
class
DecoupledDataSource
[
T
<:
Data
](
gen
:
T
,
val
size
:
Int
,
val
data
:
(
Int
)
=>
T
,
val
repeat
:
Boolean
=
true
)
extends
Module
{
println
(
"DecoupledDataSource: size = %d, repeat = %s, addrWidth = %d"
.
format
(
size
,
if
(
repeat
)
"true"
else
"false"
,
log2Ceil
(
if
(
repeat
)
size
else
size
+
1
)))
class
DecoupledDataSource
[
T
<:
Data
](
gen
:
T
,
val
size
:
Int
,
val
data
:
(
Int
)
=>
T
,
val
repeat
:
Boolean
=
true
)
(
implicit
l
:
Logging.Level
)
extends
Module
with
Logging
{
cinfo
(
"size = %d, repeat = %s, addrWidth = %d"
.
format
(
size
,
if
(
repeat
)
"true"
else
"false"
,
log2Ceil
(
if
(
repeat
)
size
else
size
+
1
)))
val
ds
=
for
(
i
<-
0
until
size
)
yield
data
(
i
)
// evaluate data to array
val
io
=
IO
(
new
DecoupledDataSourceIO
(
gen
))
// interface
...
...
@@ -35,9 +39,18 @@ class DecoupledDataSource[T <: Data](gen: T, val size : Int, val data: (Int) =>
i
:=
0.
U
}
.
otherwise
{
if
(
repeat
)
when
(
io
.
out
.
ready
&&
io
.
out
.
valid
)
{
i
:=
i
+
1.
U
}
else
when
(
io
.
out
.
ready
&&
io
.
out
.
valid
&&
i
<
size
.
U
)
{
i
:=
i
+
1.
U
}
when
(
io
.
out
.
ready
&&
io
.
out
.
valid
)
{
val
next
=
if
(
repeat
)
{
if
(
math
.
pow
(
2
,
log2Ceil
(
size
)).
toInt
==
size
)
{
i
+
1.
U
}
else
{
Mux
((
i
+
1.
U
)
<
size
.
U
,
i
+
1.
U
,
0.
U
)
}
}
else
{
Mux
(
i
<
size
.
U
,
i
+
1.
U
,
i
)
}
info
(
p
"i = $i -> $next, bits = 0x${Hexadecimal(io.out.bits.asUInt())}"
)
i
:=
next
}
}
}
miscutils/src/main/scala/Logging.scala
0 → 100644
View file @
82e7d31a
package
chisel.miscutils
import
chisel3._
import
Logging._
import
scala.util.Properties.
{
lineSeparator
=>
NL
}
trait
Logging
{
self
:
Module
=>
def
info
(
msg
:
=>
core
.
Printable
)(
implicit
level
:
Level
)
{
log
(
Level
.
Info
,
msg
)
}
def
warn
(
msg
:
=>
core
.
Printable
)(
implicit
level
:
Level
)
{
log
(
Level
.
Warn
,
msg
)
}
def
error
(
msg
:
=>
core
.
Printable
)(
implicit
level
:
Level
)
{
log
(
Level
.
None
,
msg
)
}
def
log
(
msgLevel
:
Level
,
msg
:
=>
core
.
Printable
)(
implicit
l
:
Level
)
:
Unit
=
msgLevel
match
{
case
Level
.
Info
if
(
l
==
Level
.
Info
)
=>
printf
(
p
"[INFO] $className: $msg$NL"
)
case
Level
.
Warn
if
(
l
==
Level
.
Info
||
l
==
Level
.
Warn
)
=>
printf
(
p
"[WARN] $className: $msg$NL"
)
case
Level
.
None
=>
printf
(
p
"[ERROR] $className: $msg$NL"
)
case
_
=>
()
}
def
cinfo
(
msg
:
=>
String
)(
implicit
level
:
Level
)
{
clog
(
Level
.
Info
,
msg
)
}
def
cwarn
(
msg
:
=>
String
)(
implicit
level
:
Level
)
{
clog
(
Level
.
Warn
,
msg
)
}
def
cerror
(
msg
:
=>
String
)(
implicit
level
:
Level
)
{
clog
(
Level
.
None
,
msg
)
}
def
clog
(
msgLevel
:
Level
,
msg
:
=>
String
)(
implicit
l
:
Level
)
:
Unit
=
msgLevel
match
{
case
Level
.
Info
if
(
l
==
Level
.
Info
)
=>
println
(
s
"[INFO] $className: $msg"
)
case
Level
.
Warn
if
(
l
==
Level
.
Info
||
l
==
Level
.
Warn
)
=>
println
(
s
"[WARN] $className: $msg"
)
case
Level
.
None
=>
println
(
s
"[ERROR] $className: $msg"
)
case
_
=>
()
}
private
[
this
]
final
lazy
val
className
=
self
.
getClass
.
getSimpleName
}
object
Logging
{
sealed
trait
Level
object
Level
{
final
case
object
Info
extends
Level
final
case
object
Warn
extends
Level
final
case
object
None
extends
Level
}
}
miscutils/src/test/scala/datawidthconverter/CorrectnessHarness.scala
View file @
82e7d31a
...
...
@@ -20,7 +20,8 @@ import math.pow
class
CorrectnessHarness
(
inWidth
:
Int
,
outWidth
:
Int
,
littleEndian
:
Boolean
,
delay
:
Int
=
10
)
extends
Module
{
delay
:
Int
=
10
)
(
implicit
logLevel
:
Logging.Level
)
extends
Module
{
require
(
delay
>
0
,
"delay bitwidth must be > 0"
)
val
io
=
IO
(
new
Bundle
{
val
dly
=
Input
(
UInt
(
Seq
(
log2Ceil
(
delay
),
1
).
max
.
W
))
...
...
miscutils/src/test/scala/datawidthconverter/DataWidthConverterSpec.scala
View file @
82e7d31a
...
...
@@ -6,6 +6,7 @@ import org.scalatest.prop.Checkers
import
generators._
class
DataWidthConverterSpec
extends
ChiselFlatSpec
with
Checkers
{
implicit
val
logLevel
=
Logging
.
Level
.
Warn
behavior
of
"DataWidthConverter"
it
should
"preserve data integrity in arbitrary conversions"
in
...
...
miscutils/src/test/scala/datawidthconverter/MinimalDelayHarness.scala
View file @
82e7d31a
...
...
@@ -15,7 +15,8 @@ import math.pow
**/
class
MinimalDelayHarness
(
val
inWidth
:
Int
,
val
outWidth
:
Int
,
val
littleEndian
:
Boolean
)
extends
Module
{
val
littleEndian
:
Boolean
)
(
implicit
l
:
Logging.Level
)
extends
Module
{
val
io
=
IO
(
new
Bundle
{
val
dsrc_out_valid
=
Output
(
Bool
())
val
dsrc_out_bits
=
Output
(
UInt
())
...
...
miscutils/src/test/scala/decoupleddatasource/DecoupledDataSourceSpec.scala
View file @
82e7d31a
...
...
@@ -36,6 +36,8 @@ class OutputCheck[T <: UInt](m: DecoupledDataSource[T], data: Int => Int) extend
}
class
DecoupledDataSourceSpec
extends
ChiselFlatSpec
with
Checkers
{
implicit
val
logLevel
=
Logging
.
Level
.
Warn
behavior
of
"DecoupledDataSource"
it
should
"generate random outputs correctly"
in
...
...
Jens Korinth
@jk
mentioned in commit
17f0d672
·
Mar 05, 2018
mentioned in commit
17f0d672
mentioned in commit 17f0d67240ebf5d7e1d0be9162d272b04256c47d
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