Commit 84c35860 authored by Jens Korinth's avatar Jens Korinth
Browse files

Implement a bus abstraction for TaPaSCo clocks and resets

* new interface:
  esa.cs.tu-darmstadt.de:tapasco:tapasco_clocks_resets:1.0
* bundles host, design and mem clocks and all reset kinds for easier
  connection of the subsystems
* each subsystem should instantiate a ClocksResetsSlaveBridge to access
  the ports
* the clocks and resets subsystem uses a ClocksResetsMasterBridge to
  propagate the clocks and resets
* both IPs are zero-logic direct wire thruputs; only used to allow
  bundling at interface leve
parent 15f96d39
module ClockResetsMasterBridge(
input i_host_clk,
input i_host_peripheral_resetn,
input i_host_peripheral_reset,
input i_host_interconnect_resetn,
input i_host_interconnect_reset,
input i_design_clk,
input i_design_peripheral_resetn,
input i_design_peripheral_reset,
input i_design_interconnect_resetn,
input i_design_interconnect_reset,
input i_mem_clk,
input i_mem_peripheral_resetn,
input i_mem_peripheral_reset,
input i_mem_interconnect_resetn,
input i_mem_interconnect_reset,
output o_host_clk,
output o_host_peripheral_resetn,
output o_host_peripheral_reset,
output o_host_interconnect_resetn,
output o_host_interconnect_reset,
output o_design_clk,
output o_design_peripheral_resetn,
output o_design_peripheral_reset,
output o_design_interconnect_resetn,
output o_design_interconnect_reset,
output o_mem_clk,
output o_mem_peripheral_resetn,
output o_mem_peripheral_reset,
output o_mem_interconnect_resetn,
output o_mem_interconnect_reset
);
assign o_host_clk = i_host_clk;
assign o_host_peripheral_resetn = i_host_peripheral_resetn;
assign o_host_peripheral_reset = i_host_peripheral_reset;
assign o_host_interconnect_resetn = i_host_interconnect_resetn;
assign o_host_interconnect_reset = i_host_interconnect_reset;
assign o_design_clk = i_design_clk;
assign o_design_peripheral_resetn = i_design_peripheral_resetn;
assign o_design_peripheral_reset = i_design_peripheral_reset;
assign o_design_interconnect_resetn = i_design_interconnect_resetn;
assign o_design_interconnect_reset = i_design_interconnect_reset;
assign o_mem_clk = i_mem_clk;
assign o_mem_peripheral_resetn = i_mem_peripheral_resetn;
assign o_mem_peripheral_reset = i_mem_peripheral_reset;
assign o_mem_interconnect_resetn = i_mem_interconnect_resetn;
assign o_mem_interconnect_reset = i_mem_interconnect_reset;
endmodule
# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
ipgui::add_page $IPINST -name "Page 0"
}
module ClockResetsSlaveBridge(
input i_host_clk,
input i_host_peripheral_resetn,
input i_host_peripheral_reset,
input i_host_interconnect_resetn,
input i_host_interconnect_reset,
input i_design_clk,
input i_design_peripheral_resetn,
input i_design_peripheral_reset,
input i_design_interconnect_resetn,
input i_design_interconnect_reset,
input i_mem_clk,
input i_mem_peripheral_resetn,
input i_mem_peripheral_reset,
input i_mem_interconnect_resetn,
input i_mem_interconnect_reset,
output o_host_clk,
output o_host_peripheral_resetn,
output o_host_peripheral_reset,
output o_host_interconnect_resetn,
output o_host_interconnect_reset,
output o_design_clk,
output o_design_peripheral_resetn,
output o_design_peripheral_reset,
output o_design_interconnect_resetn,
output o_design_interconnect_reset,
output o_mem_clk,
output o_mem_peripheral_resetn,
output o_mem_peripheral_reset,
output o_mem_interconnect_resetn,
output o_mem_interconnect_reset
);
assign o_host_clk = i_host_clk;
assign o_host_peripheral_resetn = i_host_peripheral_resetn;
assign o_host_peripheral_reset = i_host_peripheral_reset;
assign o_host_interconnect_resetn = i_host_interconnect_resetn;
assign o_host_interconnect_reset = i_host_interconnect_reset;
assign o_design_clk = i_design_clk;
assign o_design_peripheral_resetn = i_design_peripheral_resetn;
assign o_design_peripheral_reset = i_design_peripheral_reset;
assign o_design_interconnect_resetn = i_design_interconnect_resetn;
assign o_design_interconnect_reset = i_design_interconnect_reset;
assign o_mem_clk = i_mem_clk;
assign o_mem_peripheral_resetn = i_mem_peripheral_resetn;
assign o_mem_peripheral_reset = i_mem_peripheral_reset;
assign o_mem_interconnect_resetn = i_mem_interconnect_resetn;
assign o_mem_interconnect_reset = i_mem_interconnect_reset;
endmodule
# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
ipgui::add_page $IPINST -name "Page 0"
}
# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
ipgui::add_page $IPINST -name "Page 0"
}
<?xml version="1.0" encoding="UTF-8"?>
<spirit:busDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>esa.cs.tu-darmstadt.de</spirit:vendor>
<spirit:library>tapasco</spirit:library>
<spirit:name>tapasco_clocks_resets</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:directConnection>true</spirit:directConnection>
<spirit:isAddressable>false</spirit:isAddressable>
<spirit:maxMasters>1</spirit:maxMasters>
<spirit:maxSlaves>1</spirit:maxSlaves>
<spirit:description>Clock and reset ports of the three core clock systems: Host, Design and Memory.</spirit:description>
</spirit:busDefinition>
<?xml version="1.0" encoding="UTF-8"?>
<spirit:abstractionDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>esa.cs.tu-darmstadt.de</spirit:vendor>
<spirit:library>tapasco</spirit:library>
<spirit:name>tapasco_clocks_resets_rtl</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busType spirit:vendor="esa.cs.tu-darmstadt.de" spirit:library="tapasco" spirit:name="tapasco_clocks_resets" spirit:version="1.0"/>
<spirit:ports>
<spirit:port>
<spirit:logicalName>design_clk</spirit:logicalName>
<spirit:description>Design clock (i.e., Architecture base clock).</spirit:description>
<spirit:wire>
<spirit:qualifier>
<spirit:isClock>true</spirit:isClock>
</spirit:qualifier>
<spirit:onMaster>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>design_peripheral_resetn</spirit:logicalName>
<spirit:description>Peripheral active-low reset synced to design clock.</spirit:description>
<spirit:wire>
<spirit:qualifier>
<spirit:isReset>true</spirit:isReset>
</spirit:qualifier>
<spirit:onMaster>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:width>1</spirit:width>
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</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>design_peripheral_reset</spirit:logicalName>
<spirit:description>Peripheral active-high reset synced to design clock.</spirit:description>
<spirit:wire>
<spirit:qualifier>
<spirit:isReset>true</spirit:isReset>
</spirit:qualifier>
<spirit:onMaster>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
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</spirit:port>
<spirit:port>
<spirit:logicalName>design_interconnect_resetn</spirit:logicalName>
<spirit:description>Interconnect active-low reset synced to design clock.</spirit:description>
<spirit:wire>
<spirit:qualifier>
<spirit:isReset>true</spirit:isReset>
</spirit:qualifier>
<spirit:onMaster>
<spirit:width>1</spirit:width>
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<spirit:onSlave>
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</spirit:port>
<spirit:port>
<spirit:logicalName>design_interconnect_reset</spirit:logicalName>
<spirit:description>Interconnect active-high reset synced to design clock.</spirit:description>
<spirit:wire>
<spirit:qualifier>
<spirit:isReset>true</spirit:isReset>
</spirit:qualifier>
<spirit:onMaster>
<spirit:width>1</spirit:width>
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<spirit:onSlave>
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</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>host_clk</spirit:logicalName>
<spirit:description>Host clock (i.e., clock of host interfaces).</spirit:description>
<spirit:wire>
<spirit:qualifier>
<spirit:isClock>true</spirit:isClock>
</spirit:qualifier>
<spirit:onMaster>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:width>1</spirit:width>
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</spirit:port>
<spirit:port>
<spirit:logicalName>host_peripheral_resetn</spirit:logicalName>
<spirit:description>Peripheral active-low reset synced to host clock.</spirit:description>
<spirit:wire>
<spirit:qualifier>
<spirit:isReset>true</spirit:isReset>
</spirit:qualifier>
<spirit:onMaster>
<spirit:width>1</spirit:width>
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<spirit:port>
<spirit:logicalName>host_peripheral_reset</spirit:logicalName>
<spirit:description>Peripheral active-high reset synced to host clock.</spirit:description>
<spirit:wire>
<spirit:qualifier>
<spirit:isReset>true</spirit:isReset>
</spirit:qualifier>
<spirit:onMaster>
<spirit:width>1</spirit:width>
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<spirit:onSlave>
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</spirit:port>
<spirit:port>
<spirit:logicalName>host_interconnect_resetn</spirit:logicalName>
<spirit:description>Interconnect active-low reset synced to host clock.</spirit:description>
<spirit:wire>
<spirit:qualifier>
<spirit:isReset>true</spirit:isReset>
</spirit:qualifier>
<spirit:onMaster>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>host_interconnect_reset</spirit:logicalName>
<spirit:description>Interconnect active-high reset synced to host clock.</spirit:description>
<spirit:wire>
<spirit:qualifier>
<spirit:isReset>true</spirit:isReset>
</spirit:qualifier>
<spirit:onMaster>
<spirit:width>1</spirit:width>
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<spirit:onSlave>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>mem_clk</spirit:logicalName>
<spirit:description>Memory clock (i.e., base clock for memory subsystem).</spirit:description>
<spirit:wire>
<spirit:qualifier>
<spirit:isClock>true</spirit:isClock>
</spirit:qualifier>
<spirit:onMaster>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
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</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>mem_peripheral_resetn</spirit:logicalName>
<spirit:description>Peripheral active-low reset synced to mem clock.</spirit:description>
<spirit:wire>
<spirit:qualifier>
<spirit:isReset>true</spirit:isReset>
</spirit:qualifier>
<spirit:onMaster>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>mem_peripheral_reset</spirit:logicalName>
<spirit:description>Peripheral active-high reset synced to mem clock.</spirit:description>
<spirit:wire>
<spirit:qualifier>
<spirit:isReset>true</spirit:isReset>
</spirit:qualifier>
<spirit:onMaster>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>mem_interconnect_resetn</spirit:logicalName>
<spirit:description>Interconnect active-low reset synced to mem clock.</spirit:description>
<spirit:wire>
<spirit:qualifier>
<spirit:isReset>true</spirit:isReset>
</spirit:qualifier>
<spirit:onMaster>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>mem_interconnect_reset</spirit:logicalName>
<spirit:description>Interconnect active-high reset synced to mem clock.</spirit:description>
<spirit:wire>
<spirit:qualifier>
<spirit:isReset>true</spirit:isReset>
</spirit:qualifier>
<spirit:onMaster>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
</spirit:ports>
</spirit:abstractionDefinition>
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