Commit 8a43f455 authored by Jens Korinth's avatar Jens Korinth
Browse files

Fix problems with clocks and resets bridges

* found a way to express in IP-XACT that the interfaces are only bridged
  directly; there seems to be no way of doing this via Vivado, but since
  Xilinx is using it themselves (e.g., System Cache) I hope it'll work
* also remove interconnect_reset port, since they do not exist on the
  reset generators
parent 84c35860
......@@ -3,48 +3,39 @@ module ClockResetsMasterBridge(
input i_host_peripheral_resetn,
input i_host_peripheral_reset,
input i_host_interconnect_resetn,
input i_host_interconnect_reset,
input i_design_clk,
input i_design_peripheral_resetn,
input i_design_peripheral_reset,
input i_design_interconnect_resetn,
input i_design_interconnect_reset,
input i_mem_clk,
input i_mem_peripheral_resetn,
input i_mem_peripheral_reset,
input i_mem_interconnect_resetn,
input i_mem_interconnect_reset,
output o_host_clk,
output o_host_peripheral_resetn,
output o_host_peripheral_reset,
output o_host_interconnect_resetn,
output o_host_interconnect_reset,
output o_design_clk,
output o_design_peripheral_resetn,
output o_design_peripheral_reset,
output o_design_interconnect_resetn,
output o_design_interconnect_reset,
output o_mem_clk,
output o_mem_peripheral_resetn,
output o_mem_peripheral_reset,
output o_mem_interconnect_resetn,
output o_mem_interconnect_reset
output o_mem_interconnect_resetn
);
assign o_host_clk = i_host_clk;
assign o_host_peripheral_resetn = i_host_peripheral_resetn;
assign o_host_peripheral_reset = i_host_peripheral_reset;
assign o_host_interconnect_resetn = i_host_interconnect_resetn;
assign o_host_interconnect_reset = i_host_interconnect_reset;
assign o_design_clk = i_design_clk;
assign o_design_peripheral_resetn = i_design_peripheral_resetn;
assign o_design_peripheral_reset = i_design_peripheral_reset;
assign o_design_interconnect_resetn = i_design_interconnect_resetn;
assign o_design_interconnect_reset = i_design_interconnect_reset;
assign o_mem_clk = i_mem_clk;
assign o_mem_peripheral_resetn = i_mem_peripheral_resetn;
assign o_mem_peripheral_reset = i_mem_peripheral_reset;
assign o_mem_interconnect_resetn = i_mem_interconnect_resetn;
assign o_mem_interconnect_reset = i_mem_interconnect_reset;
endmodule
......@@ -3,48 +3,39 @@ module ClockResetsSlaveBridge(
input i_host_peripheral_resetn,
input i_host_peripheral_reset,
input i_host_interconnect_resetn,
input i_host_interconnect_reset,
input i_design_clk,
input i_design_peripheral_resetn,
input i_design_peripheral_reset,
input i_design_interconnect_resetn,
input i_design_interconnect_reset,
input i_mem_clk,
input i_mem_peripheral_resetn,
input i_mem_peripheral_reset,
input i_mem_interconnect_resetn,
input i_mem_interconnect_reset,
output o_host_clk,
output o_host_peripheral_resetn,
output o_host_peripheral_reset,
output o_host_interconnect_resetn,
output o_host_interconnect_reset,
output o_design_clk,
output o_design_peripheral_resetn,
output o_design_peripheral_reset,
output o_design_interconnect_resetn,
output o_design_interconnect_reset,
output o_mem_clk,
output o_mem_peripheral_resetn,
output o_mem_peripheral_reset,
output o_mem_interconnect_resetn,
output o_mem_interconnect_reset
output o_mem_interconnect_resetn
);
assign o_host_clk = i_host_clk;
assign o_host_peripheral_resetn = i_host_peripheral_resetn;
assign o_host_peripheral_reset = i_host_peripheral_reset;
assign o_host_interconnect_resetn = i_host_interconnect_resetn;
assign o_host_interconnect_reset = i_host_interconnect_reset;
assign o_design_clk = i_design_clk;
assign o_design_peripheral_resetn = i_design_peripheral_resetn;
assign o_design_peripheral_reset = i_design_peripheral_reset;
assign o_design_interconnect_resetn = i_design_interconnect_resetn;
assign o_design_interconnect_reset = i_design_interconnect_reset;
assign o_mem_clk = i_mem_clk;
assign o_mem_peripheral_resetn = i_mem_peripheral_resetn;
assign o_mem_peripheral_reset = i_mem_peripheral_reset;
assign o_mem_interconnect_resetn = i_mem_interconnect_resetn;
assign o_mem_interconnect_reset = i_mem_interconnect_reset;
endmodule
# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
ipgui::add_page $IPINST -name "Page 0"
}
......@@ -7,6 +7,5 @@
<spirit:directConnection>true</spirit:directConnection>
<spirit:isAddressable>false</spirit:isAddressable>
<spirit:maxMasters>1</spirit:maxMasters>
<spirit:maxSlaves>1</spirit:maxSlaves>
<spirit:description>Clock and reset ports of the three core clock systems: Host, Design and Memory.</spirit:description>
</spirit:busDefinition>
......@@ -71,22 +71,6 @@
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>design_interconnect_reset</spirit:logicalName>
<spirit:description>Interconnect active-high reset synced to design clock.</spirit:description>
<spirit:wire>
<spirit:qualifier>
<spirit:isReset>true</spirit:isReset>
</spirit:qualifier>
<spirit:onMaster>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>host_clk</spirit:logicalName>
<spirit:description>Host clock (i.e., clock of host interfaces).</spirit:description>
......@@ -151,22 +135,6 @@
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>host_interconnect_reset</spirit:logicalName>
<spirit:description>Interconnect active-high reset synced to host clock.</spirit:description>
<spirit:wire>
<spirit:qualifier>
<spirit:isReset>true</spirit:isReset>
</spirit:qualifier>
<spirit:onMaster>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>mem_clk</spirit:logicalName>
<spirit:description>Memory clock (i.e., base clock for memory subsystem).</spirit:description>
......@@ -231,21 +199,5 @@
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>mem_interconnect_reset</spirit:logicalName>
<spirit:description>Interconnect active-high reset synced to mem clock.</spirit:description>
<spirit:wire>
<spirit:qualifier>
<spirit:isReset>true</spirit:isReset>
</spirit:qualifier>
<spirit:onMaster>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
</spirit:ports>
</spirit:abstractionDefinition>
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