Commit 8e94f119 authored by Jens Korinth's avatar Jens Korinth
Browse files

Minimize DataWidthConverter logic

* direct reference of reset is discouraged
* replaced all direct references with RegInits or removed reset
* fixed overwrites of test runs (now each in separate dir)
* added test directory to cleanFiles, will be removed on sbt clean
parent d1530d38
......@@ -32,3 +32,5 @@ testForkedParallel in Test := false
scalacOptions ++= Seq("-language:implicitConversions", "-language:reflectiveCalls", "-deprecation", "-feature")
cleanFiles += baseDirectory.value / "test"
......@@ -47,58 +47,46 @@ class DataWidthConverter(val inWidth: Int,
upsize()
private def upsize() = {
val i = Reg(UInt(log2Ceil(ratio + 1).W))
val d = Reg(UInt(outWidth.W))
val i = RegInit(UInt(log2Ceil(ratio + 1).W), init = ratio.U)
val d = RegInit(UInt(outWidth.W), 0.U)
io.inq.ready := !reset && (i =/= 0.U || (io.inq.valid && io.deq.ready))
io.inq.ready := i =/= 0.U || (io.inq.valid && io.deq.ready)
io.deq.bits := d
io.deq.valid := !reset && i === 0.U
io.deq.valid := i === 0.U
when (reset) {
i := ratio.U
d := 0.U
when (io.inq.ready && io.inq.valid) {
if (littleEndian)
d := Cat(io.inq.bits, d) >> inWidth.U
else
d := (d << inWidth.U) | io.inq.bits
i := i - 1.U
}
.otherwise {
when (io.inq.ready && io.inq.valid) {
if (littleEndian)
d := Cat(io.inq.bits, d) >> inWidth.U
else
d := (d << inWidth.U) | io.inq.bits
i := i - 1.U
}
when (io.deq.valid && io.deq.ready) {
i := Mux(io.inq.valid, (ratio - 1).U, ratio.U)
}
when (io.deq.valid && io.deq.ready) {
i := Mux(io.inq.valid, (ratio - 1).U, ratio.U)
}
}
private def downsize() = {
val i = Reg(UInt(log2Ceil(ratio + 1).W))
val d = Reg(UInt(inWidth.W))
val i = RegInit(UInt(log2Ceil(ratio + 1).W), init = 0.U)
val d = RegInit(UInt(inWidth.W), init = 0.U)
io.inq.ready := !reset && (i === 0.U || (i === 1.U && io.deq.ready))
io.inq.ready := i === 0.U || (i === 1.U && io.deq.ready)
io.deq.valid := i > 0.U
if (littleEndian)
io.deq.bits := d(outWidth - 1, 0)
else
io.deq.bits := d(inWidth - 1, inWidth - outWidth)
io.deq.valid := !reset && i > 0.U
when (reset) {
i := 0.U
d := 0.U
when (i > 0.U && io.deq.ready) {
if (littleEndian)
d := d >> outWidth.U
else
d := d << outWidth.U
i := i - 1.U
}
.otherwise {
when (i > 0.U && io.deq.ready) {
if (littleEndian)
d := d >> outWidth.U
else
d := d << outWidth.U
i := i - 1.U
}
when (io.inq.ready && io.inq.valid) {
d := io.inq.bits
i := ratio.U
}
when (io.inq.ready && io.inq.valid) {
d := io.inq.bits
i := ratio.U
}
}
}
......
......@@ -15,7 +15,9 @@ class DataWidthConverterSpec extends ChiselFlatSpec with Checkers {
forAll(conversionWidthGen(inW)) { outW =>
println("Testing bitwidth conversion from %d bits -> %d bits (%s) with %d delay"
.format(inW:Int, outW:Int, if (littleEndian) "little-endian" else "big-endian", delay:Int))
Driver.execute(Array("--fint-write-vcd", "--target-dir", "test/DataWidthConverter"),
val end = if (littleEndian) "littleEndian" else "bigEndian"
val dir = s"in${inW:Int}out${outW:Int}${end}delay${delay:Int}"
Driver.execute(Array("--fint-write-vcd", "--target-dir", s"test/DataWidthConverter/$dir"),
() => new CorrectnessHarness(inW, outW, littleEndian, 1))
{ m => new CorrectnessTester(m) }
}
......@@ -26,7 +28,9 @@ class DataWidthConverterSpec extends ChiselFlatSpec with Checkers {
forAll(conversionWidthGen(inW)) { outW =>
println("Testing bitwidth conversion from %d bits -> %d bits (%s)"
.format(inW:Int, outW:Int, if (littleEndian) "little-endian" else "big-endian"))
Driver.execute(Array("--fint-write-vcd", "--target-dir", "test/DataWidthConverter"),
val end = if (littleEndian) "littleEndian" else "bigEndian"
val dir = s"in${inW:Int}out${outW:Int}${end}delay0"
Driver.execute(Array("--fint-write-vcd", "--target-dir", s"test/DataWidthConverter/$dir"),
() => new MinimalDelayHarness(inW, outW, littleEndian))
{ m => new MinimalDelayTester(m) }
}
......
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