Commit 944327d2 authored by Jens Korinth's avatar Jens Korinth
Browse files

Remove Verilog implementation of Tapasco Status Core

parent cdc16d33
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#!/usr/bin/python
str = """ 12'd%d: reg_data_out <= C_SLOT_KERNEL_ID_%d;
12'd%d: reg_data_out <= 32'hFFFFFFFF - C_SLOT_LOCAL_MEM_%d;"""
for x in range(1,129):
print str % (240 + x * 16, x, 240 + x * 16 + 4, x)
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