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Commit 944b8844 authored by Jens Korinth's avatar Jens Korinth
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WIP: Continue work on new interfaces

parent b33fa803
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arch/axi4mm/axi4mm.tcl
View file @ 944b8844
......@@ -182,7 +182,7 @@ namespace eval arch {
lappend mdist 0
}
# distribute masters round-robin on all output ports: mdist holds
# distribute masters round-robin on all output ports: mdist holds
# number of masters for each port
set j 0
for {set i 0} {$i < $no_masters} {incr i} {
......@@ -347,13 +347,13 @@ namespace eval arch {
# Connect internal clock lines.
proc arch_connect_clocks {} {
set host_aclk [platform::get_clock_reset_port "o_host_clk"]
set host_aclk [tapasco::subsystem::get_port "host" "clk"]
connect_bd_net $host_aclk [get_bd_pins -filter { NAME == "s_aclk" } -of_objects [get_bd_cells -filter {NAME =~ "in*"}]]
set design_aclk [platform::get_clock_reset_port "o_design_clk"]
set design_aclk [tapasco::subsystem::get_port "design" "clk"]
connect_bd_net $design_aclk [get_bd_pins -filter { NAME == "m_aclk" } -of_objects [get_bd_cells -filter {NAME =~ "in*"}]]
connect_bd_net $design_aclk [get_bd_pins -filter { TYPE == clk && DIR == I } -of_objects [get_bd_cells -filter {NAME =~ "target_ip_*"}]]
puts " creating clock lines ..."
set memory_aclk [platform::get_clock_reset_port "o_mem_clk"]
set memory_aclk [tapasco::subsystem::get_port "mem" "clk"]
if {[llength [get_bd_cells -filter {NAME =~ "out*"}]] > 0} {
connect_bd_net $design_aclk [get_bd_pins -filter { NAME == "s_aclk" } -of_objects [get_bd_cells -filter {NAME =~ "out*"}]]
connect_bd_net $memory_aclk [get_bd_pins -filter { NAME == "m_aclk" } -of_objects [get_bd_cells -filter {NAME =~ "out*"}]]
......@@ -362,29 +362,29 @@ namespace eval arch {
# Connect internal reset lines.
proc arch_connect_resets {} {
# create hierarchical ports for host interconnect and peripheral resets
set host_ic_arstn [platform::get_clock_reset_port "o_host_interconnect_resetn"]
set host_p_arstn [platform::get_clock_reset_port "o_host_peripheral_resetn"]
connect_bd_net $host_ic_arstn [get_bd_pins -filter { NAME == "s_interconnect_aresetn" } -of_objects [get_bd_cells -filter {NAME =~ "in*"}]]
connect_bd_net $host_p_arstn [get_bd_pins -filter { NAME == "s_peripheral_aresetn" } -of_objects [get_bd_cells -filter {NAME =~ "in*"}]]
# create hierarchical ports for design interconnect and peripheral resets
set design_ic_arstn [platform::get_clock_reset_port "o_design_interconnect_resetn"]
set design_p_arstn [platform::get_clock_reset_port "o_design_peripheral_resetn"]
connect_bd_net $design_ic_arstn [get_bd_pins -filter { NAME == "m_interconnect_aresetn" } -of_objects [get_bd_cells -filter {NAME =~ "in*"}]]
connect_bd_net $design_p_arstn [get_bd_pins -filter { NAME == "m_peripheral_aresetn" } -of_objects [get_bd_cells -filter {NAME =~ "in*"}]]
connect_bd_net $design_p_arstn [get_bd_pins -filter { TYPE == rst && DIR == I } -of_objects [get_bd_cells -filter {NAME =~ "target_ip*"}]]
# create hierarchical ports for memory interconnect and peripheral resets
set memory_ic_arstn [platform::get_clock_reset_port "o_mem_interconnect_resetn"]
set memory_p_arstn [platform::get_clock_reset_port "o_mem_peripheral_resetn"]
if {[llength [get_bd_cells -filter {NAME =~ "out*"}]] > 0} {
set outs [get_bd_cells -filter {NAME =~ "out*"}]
connect_bd_net $design_ic_arstn [get_bd_pins -filter { NAME == "s_interconnect_aresetn" } -of_objects $outs]
connect_bd_net $design_p_arstn [get_bd_pins -filter { NAME == "s_peripheral_aresetn" } -of_objects $outs]
connect_bd_net $memory_ic_arstn [get_bd_pins -filter { NAME == "m_interconnect_aresetn" } -of_objects $outs]
connect_bd_net $memory_p_arstn [get_bd_pins -filter { NAME == "m_peripheral_aresetn" } -of_objects $outs]
}
# create hierarchical ports for host interconnect and peripheral resets
set host_ic_arstn [tapasco::subsystem::get_port "host" "rst" "interconnect"]
set host_p_arstn [tapasco::subsystem::get_port "host" "rst" "peripheral" "resetn"]
connect_bd_net $host_ic_arstn [get_bd_pins -filter { NAME == "s_interconnect_aresetn" } -of_objects [get_bd_cells -filter {NAME =~ "in*"}]]
connect_bd_net $host_p_arstn [get_bd_pins -filter { NAME == "s_peripheral_aresetn" } -of_objects [get_bd_cells -filter {NAME =~ "in*"}]]
# create hierarchical ports for design interconnect and peripheral resets
set design_ic_arstn [tapasco::subsystem::get_port "design" "rst" "interconnect"]
set design_p_arstn [tapasco::subsystem::get_port "design" "rst" "peripheral" "resetn"]
connect_bd_net $design_ic_arstn [get_bd_pins -filter { NAME == "m_interconnect_aresetn" } -of_objects [get_bd_cells -filter {NAME =~ "in*"}]]
connect_bd_net $design_p_arstn [get_bd_pins -filter { NAME == "m_peripheral_aresetn" } -of_objects [get_bd_cells -filter {NAME =~ "in*"}]]
connect_bd_net $design_p_arstn [get_bd_pins -filter { TYPE == rst && DIR == I } -of_objects [get_bd_cells -filter {NAME =~ "target_ip*"}]]
# create hierarchical ports for memory interconnect and peripheral resets
set memory_ic_arstn [tapasco::subsystem::get_port "mem" "rst" "interconnect"]
set memory_p_arstn [tapasco::subsystem::get_port "mem" "rst" "peripheral" "resetn"]
if {[llength [get_bd_cells -filter {NAME =~ "out*"}]] > 0} {
set outs [get_bd_cells -filter {NAME =~ "out*"}]
connect_bd_net $design_ic_arstn [get_bd_pins -filter { NAME == "s_interconnect_aresetn" } -of_objects $outs]
connect_bd_net $design_p_arstn [get_bd_pins -filter { NAME == "s_peripheral_aresetn" } -of_objects $outs]
connect_bd_net $memory_ic_arstn [get_bd_pins -filter { NAME == "m_interconnect_aresetn" } -of_objects $outs]
connect_bd_net $memory_p_arstn [get_bd_pins -filter { NAME == "m_peripheral_aresetn" } -of_objects $outs]
}
}
# Instantiates the architecture.
......@@ -397,7 +397,7 @@ namespace eval arch {
}
# create hierarchical group
set group [platform::create_subsystem "uArch" true false]
set group [tapasco::subsystem::create "uArch"]
set instance [current_bd_instance .]
current_bd_instance $group
......
common/subsystem.tcl
View file @ 944b8844
......@@ -23,11 +23,12 @@
namespace eval subsystem {
namespace export create
namespace export get_port
namespace export get_ports
# Creates a hierarchical cell with given name and interface ports for clocks
# and resets of the three base clocks in TaPaSCo designs.
# @param is_source if true, will create output ports, otherwise input ports
proc create {name {is_source false} {prefix ""}} {
proc create {name {is_source false}} {
set instance [current_bd_instance]
set cell [create_bd_cell -type hier $name]
set intf_vlnv [tapasco::get_vlnv "tapasco_clocks_resets"]
......@@ -36,10 +37,10 @@ namespace eval subsystem {
foreach c {host design mem} {
puts " creating $c connections ..."
set clk [create_bd_pin -type clk -dir $d "${prefix}${c}_clk"]
set prstn [create_bd_pin -type rst -dir $d "${prefix}${c}_peripheral_aresetn"]
set prst [create_bd_pin -type rst -dir $d "${prefix}${c}_peripheral_areset"]
set irstn [create_bd_pin -type rst -dir $d "${prefix}${c}_interconnect_aresetn"]
set clk [create_bd_pin -type clk -dir $d "${c}_clk"]
set prstn [create_bd_pin -type rst -dir $d "${c}_peripheral_aresetn"]
set prst [create_bd_pin -type rst -dir $d "${c}_peripheral_areset"]
set irstn [create_bd_pin -type rst -dir $d "${c}_interconnect_aresetn"]
set_property CONFIG.POLARITY ACTIVE_LOW $prstn $irstn
}
......@@ -50,14 +51,14 @@ namespace eval subsystem {
proc get_ports {} {
set d [dict create]
foreach c {host design mem} {
set clk [get_bd_pins -of_objects [current_bd_instance .] -filter "NAME == ${c}_clk && TYPE == clk"]
set clk [get_bd_pins -of_objects [current_bd_instance .] -filter "NAME == ${c}_clk"]
set prstn [get_bd_pins -of_objects [current_bd_instance .] -filter "NAME == ${c}_peripheral_aresetn && TYPE == rst"]
set prst [get_bd_pins -of_objects [current_bd_instance .] -filter "NAME == ${c}_peripheral_areset && TYPE == rst"]
set irstn [get_bd_pins -of_objects [current_bd_instance .] -filter "NAME == ${c}_interconnect_aresetn && TYPE == rst"]
dict set d $c "clk" $clk
dict set d $c "rst" "peripheral" "resetn" $prstn
dict set d $c "rst" "peripheral" "reset" $prst
dict set d $c "rst" "interconnect" "resetn" $irstn
dict set d $c "rst" "interconnect" $irstn
}
return $d
}
......@@ -65,14 +66,14 @@ namespace eval subsystem {
# Returns pin of given type on the sub-block interface of the current instance.
proc get_port {args} {
if {[catch {dict get [get_ports] {*}$args} err]} {
puts "ERROR: $err"
puts "ERROR: $err $::errorInfo"
error "get_port: invalid args $args"
}
set r [dict get [get_ports] {*}$args]
if {[llength $r] == 0 || [llength $r] > 1} {
if {[catch {error "get_port: incomplete args $args: $r"} err]} {
puts "ERROR: $::errorInfo"
}
catch {error "get_port: incomplete args $args"}
puts "get_ports: [get_ports]"
error "$::errorInfo"
}
return $r
}
......
platform/common/platform.tcl
View file @ 944b8844
......@@ -34,7 +34,7 @@ namespace eval platform {
set instance [current_bd_instance]
# create mandatory subsystems
set ss_host [tapasco::subsystem::create "host"]
set ss_cnrs [tapasco::subsystem::create "clocks_and_resets" false true]
set ss_cnrs [tapasco::subsystem::create "clocks_and_resets" true]
set ss_mem [tapasco::subsystem::create "memory"]
set ss_intc [tapasco::subsystem::create "intc"]
set ss_tapasco [tapasco::subsystem::create "tapasco"]
......
platform/vc709/vc709.tcl
View file @ 944b8844
......@@ -57,9 +57,9 @@ namespace eval platform {
puts "Connecting [llength $irqs] interrupts .."
# create hierarchical ports
set s_axi [create_bd_intf_pin -mode Slave -vlnv [tapasco::get_vlnv "aximm_intf"] "S_INTC"]
set aclk [get_clock_reset_port "o_host_clk"]
set ic_aresetn [get_clock_reset_port "o_host_interconnect_resetn"]
set p_aresetn [get_clock_reset_port "o_host_peripheral_resetn"]
set aclk [tapasco::subsystem::get_port "host" "clk"]
set ic_aresetn [tapasco::subsystem::get_port "host" "rst" "interconnect"]
set p_aresetn [tapasco::subsystem::get_port "host" "rst" "peripheral" "resetn"]
set dma_irq [create_bd_pin -type "intr" -dir I "dma_irq"]
set msix_fail [create_bd_pin -dir "I" "msix_fail"]
......@@ -129,16 +129,16 @@ namespace eval platform {
# create hierarchical ports: clocks
set ddr_aclk [create_bd_pin -type "clk" -dir "O" "ddr_aclk"]
set design_clk [create_bd_pin -type "clk" -dir "O" "design_aclk"]
set pcie_aclk [get_clock_reset_port "o_host_clk"]
set design_aclk [get_clock_reset_port "o_design_clk"]
set pcie_aclk [tapasco::subsystem::get_port "host" "clk"]
set design_aclk [tapasco::subsystem::get_port "design" "clk"]
# create hierarchical ports: resets
set ddr_aresetn [create_bd_pin -type "rst" -dir "O" "ddr_aresetn"]
set design_aresetn [create_bd_pin -type "rst" -dir "O" "design_aresetn"]
set pcie_p_aresetn [get_clock_reset_port "o_host_peripheral_resetn"]
set ddr_ic_aresetn [get_clock_reset_port "o_mem_interconnect_resetn"]
set ddr_p_aresetn [get_clock_reset_port "o_mem_peripheral_resetn"]
set design_p_aresetn [get_clock_reset_port "o_design_peripheral_resetn"]
set pcie_p_aresetn [tapasco::subsystem::get_port "host" "rst" "peripheral" "resetn"]
set ddr_ic_aresetn [tapasco::subsystem::get_port "mem" "rst" "interconnect"]
set ddr_p_aresetn [tapasco::subsystem::get_port "mem" "rst" "peripheral" "resetn"]
set design_p_aresetn [tapasco::subsystem::get_port "design" "rst" "peripheral" "resetn"]
set irq [create_bd_pin -type "intr" -dir "O" "dma_irq"]
......@@ -185,7 +185,7 @@ namespace eval platform {
# connect DDR clock and reset
set ddr_clk [get_bd_pins mig/ui_clk]
connect_bd_net [get_clock_reset_port "o_mem_clk"] \
connect_bd_net [tapasco::subsystem::get_port "mem" "clk"] \
[get_bd_pins mig_ic/ACLK] \
[get_bd_pins mig_ic/M00_ACLK] \
[get_bd_pins mig_ic/S00_ACLK] \
......@@ -271,24 +271,24 @@ namespace eval platform {
connect_bd_intf_net [get_bd_intf_pins -of_objects $out_ic -filter {NAME == M02_AXI}] $m_tapasco
connect_bd_intf_net [get_bd_intf_pins -of_objects $out_ic -filter {NAME == M03_AXI}] $m_dma
connect_bd_net [get_clock_reset_port "o_host_clk"] \
connect_bd_net [tapasco::subsystem::get_port "host" "clk"] \
[get_bd_pins $out_ic/ACLK] \
[get_bd_pins -of_objects $out_ic -filter {NAME =~ S0* && TYPE == clk}] \
[get_bd_pins -of_objects $out_ic -filter {NAME =~ M01_* && TYPE == clk}]
connect_bd_net [get_clock_reset_port "o_design_clk"] \
connect_bd_net [tapasco::subsystem::get_port "design" "clk"] \
[get_bd_pins -of_objects $out_ic -filter {NAME =~ M00_* && TYPE == clk}] \
[get_bd_pins -of_objects $out_ic -filter {NAME =~ M02_* && TYPE == clk}]
connect_bd_net [get_clock_reset_port "o_mem_clk"] \
connect_bd_net [tapasco::subsystem::get_port "mem" "clk"] \
[get_bd_pins -of_objects $out_ic -filter {NAME =~ M03_* && TYPE == clk}]
connect_bd_net [get_clock_reset_port "o_host_peripheral_resetn"] \
connect_bd_net [tapasco::subsystem::get_port "host" "rst" "peripheral" "resetn"] \
[get_bd_pins $out_ic/ARESETN] \
[get_bd_pins -of_objects $out_ic -filter {NAME =~ S0* && TYPE == rst}] \
[get_bd_pins -of_objects $out_ic -filter {NAME =~ M01_* && TYPE == rst}]
connect_bd_net [get_clock_reset_port "o_design_peripheral_resetn"] \
connect_bd_net [tapasco::subsystem::get_port "design" "rst" "peripheral" "resetn"] \
[get_bd_pins -of_objects $out_ic -filter {NAME =~ M00_* && TYPE == rst}] \
[get_bd_pins -of_objects $out_ic -filter {NAME =~ M02_* && TYPE == rst}]
connect_bd_net [get_clock_reset_port "o_mem_peripheral_resetn"] \
connect_bd_net [tapasco::subsystem::get_port "mem" "rst" "peripheral" "resetn"] \
[get_bd_pins -of_objects $out_ic -filter {NAME =~ M03_* && TYPE == rst}]
set version [lindex [split [get_property VLNV [get_bd_cells axi_pcie3_0]] :] end]
......@@ -309,7 +309,7 @@ namespace eval platform {
# forward PCIe clock to external ports
connect_bd_net [get_bd_pins axi_pcie3_0/axi_aclk] $pcie_aclk
connect_bd_net [get_clock_reset_port "o_host_clk"] \
connect_bd_net [tapasco::subsystem::get_port "host" "clk"] \
[get_bd_pins mm_to_lite_dwidth/s_axi_aclk] \
[get_bd_pins mm_to_lite_proto/aclk] \
[get_bd_pins mm_to_lite_slice_before/aclk] \
......@@ -317,7 +317,7 @@ namespace eval platform {
[get_bd_pins mm_to_lite_slice_after/aclk]
connect_bd_net [get_bd_pins axi_pcie3_0/axi_aresetn] $pcie_aresetn
connect_bd_net [get_clock_reset_port "o_host_peripheral_resetn"] \
connect_bd_net [tapasco::subsystem::get_port "host" "rst" "peripheral" "resetn"] \
[get_bd_pins mm_to_lite_dwidth/s_axi_aresetn] \
[get_bd_pins mm_to_lite_proto/aresetn] \
[get_bd_pins mm_to_lite_slice_before/aresetn] \
......@@ -340,27 +340,27 @@ namespace eval platform {
set mem_rst_gen [tapasco::createResetGen "mem_rst_gen"]
# connect external ports
connect_bd_net $pcie_clk [get_bd_pins $host_rst_gen/slowest_sync_clk] [get_clock_reset_port "i_host_clk"]
connect_bd_net $pcie_clk [get_bd_pins $host_rst_gen/slowest_sync_clk] [tapasco::subsystem::get_port "host" "clk"]
connect_bd_net $pcie_aresetn [get_bd_pins $host_rst_gen/ext_reset_in]
connect_bd_net $ddr_clk [get_bd_pins $mem_rst_gen/slowest_sync_clk] [get_clock_reset_port "i_mem_clk"]
connect_bd_net $ddr_clk [get_bd_pins $mem_rst_gen/slowest_sync_clk] [tapasco::subsystem::get_port "mem" "clk"]
connect_bd_net $ddr_clk_aresetn [get_bd_pins $mem_rst_gen/ext_reset_in]
connect_bd_net $design_clk [get_bd_pins $design_rst_gen/slowest_sync_clk] [get_clock_reset_port "i_design_clk"]
connect_bd_net $design_clk [get_bd_pins $design_rst_gen/slowest_sync_clk] [tapasco::subsystem::get_port "design" "clk"]
connect_bd_net $design_clk_aresetn [get_bd_pins $design_rst_gen/ext_reset_in]
# connect to clock reset master
connect_bd_net [get_bd_pins $host_rst_gen/peripheral_aresetn] [get_clock_reset_port "i_host_peripheral_resetn"]
connect_bd_net [get_bd_pins $host_rst_gen/peripheral_reset] [get_clock_reset_port "i_host_peripheral_reset"]
connect_bd_net [get_bd_pins $host_rst_gen/interconnect_aresetn] [get_clock_reset_port "i_host_interconnect_resetn"]
connect_bd_net [get_bd_pins $host_rst_gen/peripheral_aresetn] [tapasco::subsystem::get_port "host" "rst" "peripheral" "resetn"]
connect_bd_net [get_bd_pins $host_rst_gen/peripheral_reset] [tapasco::subsystem::get_port "host" "rst" "peripheral" "reset"]
connect_bd_net [get_bd_pins $host_rst_gen/interconnect_aresetn] [tapasco::subsystem::get_port "host" "rst" "interconnect"]
connect_bd_net [get_bd_pins $design_rst_gen/peripheral_aresetn] [get_clock_reset_port "i_design_peripheral_resetn"]
connect_bd_net [get_bd_pins $design_rst_gen/peripheral_reset] [get_clock_reset_port "i_design_peripheral_reset"]
connect_bd_net [get_bd_pins $design_rst_gen/interconnect_aresetn] [get_clock_reset_port "i_design_interconnect_resetn"]
connect_bd_net [get_bd_pins $design_rst_gen/peripheral_aresetn] [tapasco::subsystem::get_port "design" "rst" "peripheral" "resetn"]
connect_bd_net [get_bd_pins $design_rst_gen/peripheral_reset] [tapasco::subsystem::get_port "design" "rst" "peripheral" "reset"]
connect_bd_net [get_bd_pins $design_rst_gen/interconnect_aresetn] [tapasco::subsystem::get_port "design" "rst" "interconnect"]
connect_bd_net [get_bd_pins $mem_rst_gen/peripheral_aresetn] [get_clock_reset_port "i_mem_peripheral_resetn"]
connect_bd_net [get_bd_pins $mem_rst_gen/peripheral_reset] [get_clock_reset_port "i_mem_peripheral_reset"]
connect_bd_net [get_bd_pins $mem_rst_gen/interconnect_aresetn] [get_clock_reset_port "i_mem_interconnect_resetn"]
connect_bd_net [get_bd_pins $mem_rst_gen/peripheral_aresetn] [tapasco::subsystem::get_port "mem" "rst" "peripheral" "resetn"]
connect_bd_net [get_bd_pins $mem_rst_gen/peripheral_reset] [tapasco::subsystem::get_port "mem" "rst" "peripheral" "reset"]
connect_bd_net [get_bd_pins $mem_rst_gen/interconnect_aresetn] [tapasco::subsystem::get_port "mem" "rst" "interconnect"]
}
proc create_mig_core {name} {
......
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