Skip to content
GitLab
Commit a1aac2d2 authored by Torben Kalkhof's avatar Torben Kalkhof Committed by Carsten Heinz
Browse files

Add QDMA IPs and fix address map 

Maps M_DMA and M_MEM_0 into correct address ranges by inserting an offset core before the NoC. This way we do not need changes in the driver infrastructure.
Adds new IPs into list.
parent 392be72c
Expand all Hide whitespace changes
Inline Side-by-side
toolflow/vivado/common/common_ip.tcl
View file @ a1aac2d2
......@@ -66,6 +66,10 @@ dict set stdcomps bram_ctrl vlnv "xilinx.com:ip:blk_mem_gen"
dict set stdcomps versal_emb_mem_gen vlnv "xilinx.com:ip:emb_mem_gen"
dict set stdcomps axi_gpio vlnv "xilinx.com:ip:axi_gpio:2.0"
dict set stdcomps qdma vlnv "xilinx.com:ip:qdma:4.0"
dict set stdcomps qdma_desc_gen vlnv "esa.informatik.tu-darmstadt.de:user:QDMADescriptorGenerator:1.0"
dict set stdcomps qdma_configurator vlnv "esa.informatik.tu-darmstadt.de:user:QDMAConfigurator:1.0"
dict set stdcomps qdma_intr_ctrl vlnv "esa.informatik.tu-darmstadt.de:user:QDMAIntrCtrl:1.0"
dict set stdcomps axi_generic_off vlnv "esa.informatik.tu-darmstadt.de:user:axi_generic_offset:0.1"
dict set stdcomps axioffset_hbm vlnv "esa.informatik.tu-darmstadt.de:user:AXIOffsetHBM:1.0"
dict set stdcomps sume_clock_prog vlnv "esa.informatik.tu-darmstadt.de:user:SumeClockProgrammer:1.0"
dict set stdcomps dmi vlnv "esa.informatik.tu-darmstadt.de:user:DMI_rtl:1.0"
......
toolflow/vivado/common/ip/axi_generic_offset/component.xml 0 → 100644
View file @ a1aac2d2
This diff is collapsed.
toolflow/vivado/common/ip/axi_generic_offset/src/axi_generic_offset.v 0 → 100755
View file @ a1aac2d2
/*
* AXI offset. Set highest address bit to zero.
*
* Author: Carsten Heinz <heinz@esa.tu-darmstadt.de>
* Copyright (c) 2018 Embedded Systems and Applications Group, TU Darmstadt
*/
`default_nettype none
module axi_generic_offset #(
parameter BYTES_PER_WORD = 16,
parameter ADDRESS_WIDTH = 32,
parameter ID_WIDTH = 6,
parameter OVERWRITE_BITS = 1,
parameter HIGHEST_ADDR_BIT = 0
) (
input wire aclk,
input wire aresetn,
input wire [ADDRESS_WIDTH-1:0] S_AXI_araddr,
input wire [7:0] S_AXI_arlen,
input wire [2:0] S_AXI_arprot,
input wire [2:0] S_AXI_arsize,
input wire [1:0] S_AXI_arburst,
input wire S_AXI_arlock,
input wire [3:0] S_AXI_arcache,
input wire [3:0] S_AXI_arqos,
input wire [3:0] S_AXI_arregion,
input wire S_AXI_aruser,
input wire [ID_WIDTH-1:0] S_AXI_arid,
output wire S_AXI_arready,
input wire S_AXI_arvalid,
input wire [ADDRESS_WIDTH-1:0] S_AXI_awaddr,
input wire [7:0] S_AXI_awlen,
input wire [2:0] S_AXI_awprot,
input wire [2:0] S_AXI_awsize,
input wire [1:0] S_AXI_awburst,
input wire S_AXI_awlock,
input wire [3:0] S_AXI_awcache,
input wire [3:0] S_AXI_awqos,
input wire [3:0] S_AXI_awregion,
input wire S_AXI_awuser,
input wire [ID_WIDTH-1:0] S_AXI_awid,
output wire S_AXI_awready,
input wire S_AXI_awvalid,
input wire S_AXI_bready,
output wire S_AXI_bvalid,
output wire [ID_WIDTH-1:0] S_AXI_bid,
output wire [1:0] S_AXI_bresp,
output wire S_AXI_buser,
output wire [BYTES_PER_WORD*8-1:0] S_AXI_rdata,
output wire S_AXI_rlast,
input wire S_AXI_rready,
output wire S_AXI_rvalid,
output wire [ID_WIDTH-1:0] S_AXI_rid,
output wire [1:0] S_AXI_rresp,
output wire S_AXI_ruser,
input wire [BYTES_PER_WORD*8-1:0] S_AXI_wdata,
input wire [BYTES_PER_WORD-1:0] S_AXI_wstrb,
input wire S_AXI_wlast,
output wire S_AXI_wready,
input wire S_AXI_wvalid,
output wire [ADDRESS_WIDTH-1:0] M_AXI_araddr,
output wire [7:0] M_AXI_arlen,
output wire [2:0] M_AXI_arprot,
output wire [2:0] M_AXI_arsize,
output wire [1:0] M_AXI_arburst,
output wire M_AXI_arlock,
output wire [3:0] M_AXI_arcache,
output wire [3:0] M_AXI_arqos,
output wire [3:0] M_AXI_arregion,
output wire M_AXI_aruser,
output wire [ID_WIDTH-1:0] M_AXI_arid,
input wire M_AXI_arready,
output wire M_AXI_arvalid,
output wire [ADDRESS_WIDTH-1:0] M_AXI_awaddr,
output wire [7:0] M_AXI_awlen,
output wire [2:0] M_AXI_awprot,
output wire [2:0] M_AXI_awsize,
output wire [1:0] M_AXI_awburst,
output wire M_AXI_awlock,
output wire [3:0] M_AXI_awcache,
output wire [3:0] M_AXI_awqos,
output wire [3:0] M_AXI_awregion,
output wire M_AXI_awuser,
output wire [ID_WIDTH-1:0] M_AXI_awid,
input wire M_AXI_awready,
output wire M_AXI_awvalid,
output wire M_AXI_bready,
input wire M_AXI_bvalid,
input wire [ID_WIDTH-1:0] M_AXI_bid,
input wire [1:0] M_AXI_bresp,
input wire M_AXI_buser,
input wire [BYTES_PER_WORD*8-1:0] M_AXI_rdata,
input wire M_AXI_rlast,
output wire M_AXI_rready,
input wire M_AXI_rvalid,
input wire [ID_WIDTH-1:0] M_AXI_rid,
input wire [1:0] M_AXI_rresp,
input wire M_AXI_ruser,
output wire [BYTES_PER_WORD*8-1:0] M_AXI_wdata,
output wire [BYTES_PER_WORD-1:0] M_AXI_wstrb,
output wire M_AXI_wlast,
input wire M_AXI_wready,
output wire M_AXI_wvalid
);
assign M_AXI_araddr = {HIGHEST_ADDR_BIT[OVERWRITE_BITS-1:0],S_AXI_araddr[ADDRESS_WIDTH-OVERWRITE_BITS-1:0]};
assign M_AXI_arlen = S_AXI_arlen;
// overwrite arprot with "Secure Data Unpriviledged" to prevent DECERR returned by memory controller of the PYNQ
assign M_AXI_arprot = 3'b000;
assign M_AXI_arsize = S_AXI_arsize;
assign M_AXI_arburst = S_AXI_arburst;
assign M_AXI_arlock = S_AXI_arlock;
assign M_AXI_arcache = S_AXI_arcache;
assign M_AXI_arqos = S_AXI_arqos;
assign M_AXI_arregion = S_AXI_arregion;
assign M_AXI_aruser = S_AXI_aruser;
assign M_AXI_arid = S_AXI_arid;
assign M_AXI_arvalid = S_AXI_arvalid;
assign M_AXI_awaddr = {HIGHEST_ADDR_BIT[OVERWRITE_BITS-1:0],S_AXI_awaddr[ADDRESS_WIDTH-OVERWRITE_BITS-1:0]};
assign M_AXI_awlen = S_AXI_awlen;
// overwrite awprot with "Secure Data Unpriviledged" to prevent DECERR returned by memory controller of the PYNQ
assign M_AXI_awprot = 3'b000;
assign M_AXI_awsize = S_AXI_awsize;
assign M_AXI_awburst = S_AXI_awburst;
assign M_AXI_awlock = S_AXI_awlock;
assign M_AXI_awcache = S_AXI_awcache;
assign M_AXI_awqos = S_AXI_awqos;
assign M_AXI_awregion = S_AXI_awregion;
assign M_AXI_awuser = S_AXI_awuser;
assign M_AXI_awid = S_AXI_awid;
assign M_AXI_awvalid = S_AXI_awvalid;
assign M_AXI_bready = S_AXI_bready;
assign S_AXI_bid = M_AXI_bid;
assign S_AXI_bresp = M_AXI_bresp;
assign S_AXI_buser = M_AXI_buser;
assign M_AXI_rready = S_AXI_rready;
assign M_AXI_wdata = S_AXI_wdata;
assign M_AXI_wstrb = S_AXI_wstrb;
assign M_AXI_wlast = S_AXI_wlast;
assign M_AXI_wvalid = S_AXI_wvalid;
assign S_AXI_arready = M_AXI_arready;
assign S_AXI_awready = M_AXI_awready;
assign S_AXI_bvalid = M_AXI_bvalid;
assign S_AXI_rdata = M_AXI_rdata;
assign S_AXI_rlast = M_AXI_rlast;
assign S_AXI_rvalid = M_AXI_rvalid;
assign S_AXI_rid = M_AXI_rid;
assign S_AXI_rresp = M_AXI_rresp;
assign S_AXI_ruser = M_AXI_ruser;
assign S_AXI_wready = M_AXI_wready;
endmodule
`default_nettype wire
toolflow/vivado/common/ip/axi_generic_offset/xgui/axi_generic_offset_v0_1.tcl 0 → 100644
View file @ a1aac2d2
# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
ipgui::add_param $IPINST -name "ADDRESS_WIDTH" -parent ${Page_0}
ipgui::add_param $IPINST -name "BYTES_PER_WORD" -parent ${Page_0}
ipgui::add_param $IPINST -name "HIGHEST_ADDR_BIT" -parent ${Page_0}
ipgui::add_param $IPINST -name "ID_WIDTH" -parent ${Page_0}
ipgui::add_param $IPINST -name "OVERWRITE_BITS" -parent ${Page_0}
}
proc update_PARAM_VALUE.ADDRESS_WIDTH { PARAM_VALUE.ADDRESS_WIDTH } {
# Procedure called to update ADDRESS_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.ADDRESS_WIDTH { PARAM_VALUE.ADDRESS_WIDTH } {
# Procedure called to validate ADDRESS_WIDTH
return true
}
proc update_PARAM_VALUE.BYTES_PER_WORD { PARAM_VALUE.BYTES_PER_WORD } {
# Procedure called to update BYTES_PER_WORD when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.BYTES_PER_WORD { PARAM_VALUE.BYTES_PER_WORD } {
# Procedure called to validate BYTES_PER_WORD
return true
}
proc update_PARAM_VALUE.HIGHEST_ADDR_BIT { PARAM_VALUE.HIGHEST_ADDR_BIT } {
# Procedure called to update HIGHEST_ADDR_BIT when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.HIGHEST_ADDR_BIT { PARAM_VALUE.HIGHEST_ADDR_BIT } {
# Procedure called to validate HIGHEST_ADDR_BIT
return true
}
proc update_PARAM_VALUE.ID_WIDTH { PARAM_VALUE.ID_WIDTH } {
# Procedure called to update ID_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.ID_WIDTH { PARAM_VALUE.ID_WIDTH } {
# Procedure called to validate ID_WIDTH
return true
}
proc update_PARAM_VALUE.OVERWRITE_BITS { PARAM_VALUE.OVERWRITE_BITS } {
# Procedure called to update OVERWRITE_BITS when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.OVERWRITE_BITS { PARAM_VALUE.OVERWRITE_BITS } {
# Procedure called to validate OVERWRITE_BITS
return true
}
proc update_MODELPARAM_VALUE.BYTES_PER_WORD { MODELPARAM_VALUE.BYTES_PER_WORD PARAM_VALUE.BYTES_PER_WORD } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.BYTES_PER_WORD}] ${MODELPARAM_VALUE.BYTES_PER_WORD}
}
proc update_MODELPARAM_VALUE.ADDRESS_WIDTH { MODELPARAM_VALUE.ADDRESS_WIDTH PARAM_VALUE.ADDRESS_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.ADDRESS_WIDTH}] ${MODELPARAM_VALUE.ADDRESS_WIDTH}
}
proc update_MODELPARAM_VALUE.ID_WIDTH { MODELPARAM_VALUE.ID_WIDTH PARAM_VALUE.ID_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.ID_WIDTH}] ${MODELPARAM_VALUE.ID_WIDTH}
}
proc update_MODELPARAM_VALUE.OVERWRITE_BITS { MODELPARAM_VALUE.OVERWRITE_BITS PARAM_VALUE.OVERWRITE_BITS } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.OVERWRITE_BITS}] ${MODELPARAM_VALUE.OVERWRITE_BITS}
}
proc update_MODELPARAM_VALUE.HIGHEST_ADDR_BIT { MODELPARAM_VALUE.HIGHEST_ADDR_BIT PARAM_VALUE.HIGHEST_ADDR_BIT } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.HIGHEST_ADDR_BIT}] ${MODELPARAM_VALUE.HIGHEST_ADDR_BIT}
}
toolflow/vivado/platform/versal/versal_base.tcl
View file @ a1aac2d2
......@@ -181,7 +181,7 @@
# TODO: Make configuration device dependent
set qdma_desc [create_bd_cell -type ip -vlnv esa.informatik.tu-darmstadt.de:user:QDMADescriptorGenerator:1.0 QDMADescriptorGenera_0]
set qdma_desc [tapasco::ip::create_qdma_desc_gen "QDMADescriptorGenera_0"]
connect_bd_intf_net $s_desc_gen $qdma_desc/S_AXI_CTRL
connect_bd_intf_net $qdma_desc/c2h_byp_in $qdma/c2h_byp_in_mm
connect_bd_intf_net $qdma_desc/h2c_byp_in $qdma/h2c_byp_in_mm
......@@ -190,7 +190,7 @@
connect_bd_intf_net $qdma_desc/c2h_byp_out $qdma/c2h_byp_out
connect_bd_intf_net $qdma_desc/h2c_byp_out $qdma/h2c_byp_out
set qdma_conf [create_bd_cell -type ip -vlnv esa.informatik.tu-darmstadt.de:user:QDMAConfigurator:1.0 QDMAConfigurator_0]
set qdma_conf [tapasco::ip::create_qdma_configurator "QDMAConfigurator_0"]
connect_bd_intf_net [get_bd_intf_pins $qdma_conf/msix_vector_ctrl] [get_bd_intf_pins $qdma/msix_vector_ctrl]
connect_bd_intf_net $qdma/M_AXI $m_dma
......@@ -214,7 +214,18 @@
proc create_subsystem_memory {} {
# memory subsystem implements the NoC logic and Memory Controller
set host_aclk [tapasco::subsystem::get_port "host" "clk"]
set host_p_aresetn [tapasco::subsystem::get_port "host" "rst" "peripheral" "resetn"]
set design_aclk [tapasco::subsystem::get_port "design" "clk"]
set design_aresetn [tapasco::subsystem::get_port "design" "rst" "peripheral" "resetn"]
set s_axi_mem [create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 "S_MEM_0"]
set s_axi_dma [create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 "S_DMA"]
set s_axi_mem_off [create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 "S_MEM_0_OFF"]
set s_axi_dma_off [create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 "S_DMA_OFF"]
set m_axi_mem_off [create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 "M_MEM_0_OFF"]
set m_axi_dma_off [create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 "M_DMA_OFF"]
set versal_cips [tapasco::ip::create_versal_cips "versal_cips_0"]
# set versal_cips [ create_bd_cell -type ip -vlnv xilinx.com:ip:versal_cips:3.1 versal_cips_0 ]
set_property -dict [ list \
......@@ -256,6 +267,31 @@
CONFIG.PS_PMC_CONFIG_APPLIED {1} \
] $versal_cips
# offset to map memory request from QDMA or PEs into address range of memory controllers
set dma_sc [tapasco::ip::create_axi_sc "dma_sc_0" 1 1 1]
set dma_offset [tapasco::ip::create_axi_generic_off "dma_offset_0"]
set_property -dict [list CONFIG.ADDRESS_WIDTH {41} \
CONFIG.BYTES_PER_WORD {64} \
CONFIG.HIGHEST_ADDR_BIT {1} \
CONFIG.ID_WIDTH {4} \
CONFIG.OVERWRITE_BITS {1} ] $dma_offset
set arch_offset [tapasco::ip::create_axi_generic_off "arch_offset_0"]
set_property -dict [list CONFIG.ADDRESS_WIDTH {41} \
CONFIG.BYTES_PER_WORD {64} \
CONFIG.HIGHEST_ADDR_BIT {1} \
CONFIG.ID_WIDTH {6} \
CONFIG.OVERWRITE_BITS {1} ] $arch_offset
connect_bd_net $design_aclk [get_bd_pin $arch_offset/aclk]
connect_bd_net $host_aclk [get_bd_pin $dma_offset/aclk] [get_bd_pin $dma_sc/aclk]
connect_bd_net $design_aresetn [get_bd_pin $arch_offset/aresetn]
connect_bd_net $host_p_aresetn [get_bd_pin $dma_offset/aresetn]
connect_bd_intf_net $s_axi_dma [get_bd_intf_pin $dma_sc/S00_AXI]
connect_bd_intf_net [get_bd_intf_pin $dma_sc/M00_AXI] [get_bd_intf_pin $dma_offset/S_AXI]
connect_bd_intf_net [get_bd_intf_pin $dma_offset/M_AXI] $m_axi_dma_off
connect_bd_intf_net $s_axi_mem [get_bd_intf_pin $arch_offset/S_AXI]
connect_bd_intf_net [get_bd_intf_pin $arch_offset/M_AXI] $m_axi_mem_off
set axi_noc [tapasco::ip::create_axi_noc "axi_noc_0"]
set external_sources {2}
# Possible values: None, 1, 2, ...
......@@ -277,12 +313,10 @@
delete_bd_objs [get_bd_nets /memory/aclk1_0_1] [get_bd_pins /memory/aclk1_0]
# S00_AXI -> S_MEM_0
# S01_AXI -> S_DMA
set s_axi_mem [create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 "S_MEM_0"]
set s_axi_dma [create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 "S_DMA"]
connect_bd_intf_net $s_axi_mem $axi_noc/S00_AXI
connect_bd_intf_net $s_axi_dma $axi_noc/S01_AXI
connect_bd_net [tapasco::subsystem::get_port "design" "clk"] [get_bd_pin $axi_noc/aclk1]
connect_bd_net [tapasco::subsystem::get_port "host" "clk"] [get_bd_pin $axi_noc/aclk7]
connect_bd_intf_net $s_axi_mem_off $axi_noc/S00_AXI
connect_bd_intf_net $s_axi_dma_off $axi_noc/S01_AXI
connect_bd_net $design_aclk [get_bd_pin $axi_noc/aclk1]
connect_bd_net $host_aclk [get_bd_pin $axi_noc/aclk7]
set_property -dict [list CONFIG.ASSOCIATED_BUSIF {S02_AXI}] [get_bd_pins $axi_noc/aclk0]
set_property -dict [list CONFIG.ASSOCIATED_BUSIF {S00_AXI}] [get_bd_pins $axi_noc/aclk1]
set_property -dict [list CONFIG.ASSOCIATED_BUSIF {S01_AXI}] [get_bd_pins $axi_noc/aclk7]
......@@ -350,18 +384,18 @@
}
}
set QDMAIntrCtrl [create_bd_cell -type ip -vlnv esa.informatik.tu-darmstadt.de:user:QDMAIntrCtrl:1.0 QDMAIntrCtrl_0]
set qdma_intr_ctrl [tapasco::ip::create_qdma_intr_ctrl "QDMAIntrCtrl_0"]
connect_bd_intf_net $QDMAIntrCtrl/S_AXI $s_axi
connect_bd_intf_net $qdma_intr_ctrl/S_AXI $s_axi
connect_bd_net [get_bd_pins ${design_concats_last}/dout] [get_bd_pins $QDMAIntrCtrl/interrupt_design]
connect_bd_net [get_bd_pins ${design_concats_last}/dout] [get_bd_pins $qdma_intr_ctrl/interrupt_design]
connect_bd_net $design_aclk [get_bd_pins $QDMAIntrCtrl/design_clk]
connect_bd_net $design_aresetn [get_bd_pins $QDMAIntrCtrl/design_rst]
connect_bd_net $host_aclk [get_bd_pins $QDMAIntrCtrl/S_AXI_aclk]
connect_bd_net $host_p_aresetn [get_bd_pins $QDMAIntrCtrl/S_AXI_aresetn]
connect_bd_net $design_aclk [get_bd_pins $qdma_intr_ctrl/design_clk]
connect_bd_net $design_aresetn [get_bd_pins $qdma_intr_ctrl/design_rst]
connect_bd_net $host_aclk [get_bd_pins $qdma_intr_ctrl/S_AXI_aclk]
connect_bd_net $host_p_aresetn [get_bd_pins $qdma_intr_ctrl/S_AXI_aresetn]
connect_bd_intf_net $QDMAIntrCtrl/usr_irq /host/qdma_0/usr_irq
connect_bd_intf_net $qdma_intr_ctrl/usr_irq /host/qdma_0/usr_irq
}
proc get_pe_base_address {} {
......@@ -382,10 +416,13 @@
set masters [::tapasco::get_aximm_interfaces [get_bd_cells -filter "PATH !~ [::tapasco::subsystem::get arch]/*"]]
foreach m $masters {
switch -glob [get_property NAME $m] {
"M_INTC" { foreach {base stride range comp} [list [expr [get_platform_base_address]+0x20000] 0x10000 0 "PLATFORM_COMPONENT_INTC0" ] {} }
"M_TAPASCO" { foreach {base stride range comp} [list [get_platform_base_address] 0x10000 0 "PLATFORM_COMPONENT_STATUS"] {} }
"M_DESC_GEN" { foreach {base stride range comp} [list [expr [get_platform_base_address]+0x10000] 0x10000 0 "PLATFORM_COMPONENT_DMA0" ] {} }
"M_DMA" { foreach {base stride range comp} [list [expr "1 << 40"] 0 [expr "1 << 37"] "" ] {} }
"M_INTC" { foreach {base stride range comp} [list [expr [get_platform_base_address]+0x20000] 0x10000 0 "PLATFORM_COMPONENT_INTC0" ] {} }
"M_TAPASCO" { foreach {base stride range comp} [list [get_platform_base_address] 0x10000 0 "PLATFORM_COMPONENT_STATUS"] {} }
"M_DESC_GEN" { foreach {base stride range comp} [list [expr [get_platform_base_address]+0x10000] 0x10000 0 "PLATFORM_COMPONENT_DMA0" ] {} }
"M_DMA" { foreach {base stride range comp} [list 0 0 [expr "1 << 37"] "" ] {} }
"M_DMA_OFF" { foreach {base stride range comp} [list [expr "1 << 40"] 0 [expr "1 << 37"] "" ] {} }
"M_MEM_0" { foreach {base stride range comp} [list 0 0 [expr "1 << 37"] "" ] {} }
"M_MEM_0_OFF" { foreach {base stride range comp} [list [expr "1 << 40"] 0 [expr "1 << 37"] "" ] {} }
"M_ARCH" { set base "skip" }
default { if { [dict exists $extra_masters [get_property NAME $m]] } {
set l [dict get $extra_masters [get_property NAME $m]]
......@@ -406,7 +443,7 @@
proc get_ignored_segments {} {
set ignored [list]
lappend ignored "/memory/axi_noc_0/S00_AXI/C0_DDR_LOW3x4"
# lappend ignored "/memory/axi_noc_0/S00_AXI/C0_DDR_LOW3x4"
lappend ignored "/memory/axi_noc_0/S01_AXI/C0_DDR_LOW3x4"
lappend ignored "/memory/axi_noc_0/S02_AXI/C0_DDR_LOW3x4"
lappend ignored "/memory/axi_noc_0/S03_AXI/C0_DDR_LOW3x4"
......
Supports Markdown
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment