Squashed 'packaging/' changes from 7854cfd1..5a3d0f79

5a3d0f79 Postfix issue, feature warnings activated
fc967e4c Update to Scala 2.11.11
ad1c4c32 Support for manual AXI-mapping, postBuildOps fix
fa4bfbeb Fix README.md markdown syntax

git-subtree-dir: packaging
git-subtree-split: 5a3d0f79

CoreDefinition.scala

@@ -4,11 +4,15 @@ import  play.api.libs.json._
 import  play.api.libs.functional.syntax._
 import  chisel3.Module
 
+/** Abstraction for known bus interfaces / pin groups. */
+final case class Interface(name: String, kind: String)
+
 /**
  * Basic definition of a core for IP-XACT packaging.
  **/
 class CoreDefinition(val name: String, val vendor: String, val library: String, val version: String,
-                     val root: String, val postBuildActions: Seq[Module => Unit] = Seq()) {
+                     val root: String, val postBuildActions: Seq[Option[Any] => Unit] = Seq(),
+                     val interfaces: Seq[Interface] = Seq()) {
   import CoreDefinition._
   def write(filename: String) : Boolean = try {
     val fw = new java.io.FileWriter(filename)
@@ -23,35 +27,43 @@ class CoreDefinition(val name: String, val vendor: String, val library: String,
  * Contains methods for reading a core definition from Json.
  **/
 object CoreDefinition {
-  def apply(name: String, vendor: String, library: String, version: String, root: String): CoreDefinition =
-    new CoreDefinition(name, vendor, library, version, root)
+  def apply(name: String, vendor: String, library: String, version: String, root: String,
+            interfaces: Seq[Interface] = Seq()): CoreDefinition =
+    new CoreDefinition(name, vendor, library, version, root, interfaces = interfaces)
 
   def withActions(name: String, vendor: String, library: String, version: String, root: String,
-            postBuildActions: Seq[Module => Unit]): CoreDefinition =
+                  postBuildActions: Seq[Option[Any] => Unit], interfaces: Seq[Interface] = Seq()): CoreDefinition =
     new CoreDefinition(name, vendor, library, version, root, postBuildActions)
 
-  def unapply(cd: CoreDefinition): Option[Tuple5[String, String, String, String, String]] =
-    Some((cd.name, cd.vendor, cd.library, cd.version, cd.root))
+  def unapply(cd: CoreDefinition): Option[Tuple6[String, String, String, String, String, Seq[Interface]]] =
+    Some((cd.name, cd.vendor, cd.library, cd.version, cd.root, cd.interfaces))
 
   /** Provide automatic IP directory for given name. **/
   def root(name: String): String =
       java.nio.file.Paths.get(".").toAbsolutePath.resolveSibling("ip").resolve(name).toString
 
-  implicit val coreDefinitionWrites : Writes[CoreDefinition] = (
+  implicit val interfaceFormat: Format[Interface] = (
+    (JsPath \ "name").format[String] ~
+    (JsPath \ "kind").format[String]
+  ) (Interface.apply _, unlift(Interface.unapply _))
+
+  implicit val coreDefinitionWrites: Writes[CoreDefinition] = (
       (JsPath \ "name").write[String] ~
       (JsPath \ "vendor").write[String] ~
       (JsPath \ "library").write[String] ~
       (JsPath \ "version").write[String] ~
-      (JsPath \ "root").write[String]
-    )(unlift(CoreDefinition.unapply))
+      (JsPath \ "root").write[String] ~
+      (JsPath \ "interfaces").write[Seq[Interface]]
+    )(unlift(CoreDefinition.unapply _))
 
-  implicit val coreDefinitionReads : Reads[CoreDefinition] = (
+  implicit val coreDefinitionReads: Reads[CoreDefinition] = (
       (JsPath \ "name").read[String] ~
       (JsPath \ "vendor").read[String] ~
       (JsPath \ "library").read[String] ~
       (JsPath \ "version").read[String] ~
-      (JsPath \ "root").read[String]
-    )(CoreDefinition.apply _)
+      (JsPath \ "root").read[String] ~
+      (JsPath \ "interfaces").readNullable[Seq[Interface]].map(_ getOrElse Seq[Interface]())
+    )(apply _)
 
   /**
    * Read CoreDefinition from file containing Json format.

ModuleBuilder.scala

@@ -2,6 +2,13 @@ package chisel.packaging
 import  chisel3._
 import  scala.sys.process._
 
+/** Module definition.
+ *  @param config Optional, arbitrary configuration object, passed to post build actions.
+ *  @param constr Module constructor function.
+ *  @param core   Core definition.
+ **/
+final case class ModuleDef(config: Option[Any], constr: () => Module, core: CoreDefinition)
+
 /**
  * Abstract IP-XACT builder class:
  * Objects can inherit from ModuleBuilder to automate the building
@@ -12,18 +19,19 @@ import  scala.sys.process._
  **/
 abstract class ModuleBuilder(packagingDir: String = "packaging") {
   val chiselArgs = Array[String]()
-  val modules: List[(() => Module, CoreDefinition)]
+  /** List of modules to build. */
+  val modules: Seq[ModuleDef]
 
   def main(args: Array[String]) {
-    assert ((modules map (_._2.name.toLowerCase)).toSet.size == modules.length, "module names must be unique")
-    val fm = modules filter (m => args.length == 0 || args.map(_.toLowerCase).contains(m._2.name.toLowerCase))
+    assert ((modules map (_.core.name.toLowerCase)).toSet.size == modules.length, "module names must be unique")
+    val fm = modules filter (m => args.length == 0 || args.map(_.toLowerCase).contains(m.core.name.toLowerCase))
     assert (fm.length > 0, "no matching cores found for: " + args.mkString(", "))
     fm foreach { m =>
-      Driver.execute(chiselArgs ++ Array("--target-dir", m._2.root), m._1)
-      m._2.postBuildActions map (fn => fn.apply(m._1()))
-      val json = "%s/%s.json".format(m._2.root, m._2.name)
-      m._2.write(json)
-      "%s/package.py %s".format(packagingDir, json) !
+      Driver.execute(chiselArgs ++ Array("--target-dir", m.core.root), m.constr)
+      m.core.postBuildActions map (fn => fn.apply(m.config))
+      val json = "%s/%s.json".format(m.core.root, m.core.name)
+      m.core.write(json)
+      "%s/package.py %s".format(packagingDir, json).!
     }
   }
 }

README.md

@@ -8,26 +8,28 @@ did not fit your needs.
 
 Requirements
 ----------------------
-  * Vivado 2016.x+
-  * Chisel 3.x *(currently using `3.0-SNAPSHOT`)*
-  * *optional*: sbt
+
+*   Vivado 2016.x+
+*   Chisel 3.x *(currently using `3.0-SNAPSHOT`)*
+*   *optional*: sbt
 
 Basic Usage
 -----------
+
 Class `ModuleBuilder` provides an abstract base class for an executable object with a `main`
 method. You'll only need to provide a list of Chisel cores you'd like to wrap into IP-XACT.
 A full example can be found in `example`; test it as follows:
 
-  1. Source the Vivado settings scripts, make sure `vivado` is in the `PATH`.
-  2. In the `chisel-packaging` base dir, do:  
-        
+1.   Source the Vivado settings scripts, make sure `vivado` is in the `PATH`.
+2.   In the `chisel-packaging` base dir, do:  
+      
         cp example/* .
         
-  3. Execute via:
+3.   Execute via:
         
         sbt run
         
-  4. This should create a new directory `ip`, which contains subdirectories for each core.
+4.   This should create a new directory `ip`, which contains subdirectories for each core.
      The subdirectories contain the Verilog sources and the IP-XACT `component.xml`.
 
 You can use the `ip` directory as a base directory for user IP in Vivado, the cores should
@@ -36,41 +38,43 @@ automatically appear in Vivado and IP-Integrator.
 
 Usage in Chisel Projects (*sbt*)
 --------------------------------
+
 The easiest way to setup `chisel-packaging` for your Chisel project with `sbt` is using
 **git subtree** ([this article] [1] has an excellent intro to subtrees) as follows:
 
-  1. In your the base directory of your project, add a new remote *chisel-packaging*:
+1.   In your the base directory of your project, add a new remote *chisel-packaging*:
         
         git remote add chisel-packaging https://bitbucket.org/jkorinth/chisel-packaging.git
         
-  2. Setup a subtree in `packaging`:
-        
+2.   Setup a subtree in `packaging`:
+       
         git subtree add --prefix packaging chisel-packaging master --squash
-        
+      
     This will clone the `chisel-packaging` into the `packaging` folder.
-
-  3. Add a project dependency in your `build.sbt`, add lines:
+    
+3.   Add a project dependency in your `build.sbt`, add lines:
         
         lazy val packaging = project.in(file("packaging"))
         
         lazy val root = (project in file(".")).dependsOn(packaging)
         
-
+    
     *Note that the empty lines are **not optional** - a quirk of sbt.*
-
-  4. Implement `chisel.packaging.ModuleBuilder` in your own code; if you've chosen
+    
+4.   Implement `chisel.packaging.ModuleBuilder` in your own code; if you've chosen
      a different directory than `packaging` for the subtree, you can pass it to the
      baseclass constructor -- see [example/ModuleBuilderTest.scala][3]
-
-  5. Build the IP-XACT cores via `sbt run`.
+     
+5.   Build the IP-XACT cores via `sbt run`.
 
 Gotchas
 -------
-  * The python script requires `vivado` to be in `PATH`, so you need to source the Vivado
+
+*   The python script requires `vivado` to be in `PATH`, so you need to source the Vivado
     settings scripts first.
-  * The repo is setup for Chisel 3.x; it can be used for Chisel 2.x, but that requires
+*   The repo is setup for Chisel 3.x; it can be used for Chisel 2.x, but that requires
     manual changes - open an issue in the issue tracker if you need it.
-  * If you're using the `sbt` approach outlined above, make sure your `build.sbt` contains
+*   If you're using the `sbt` approach outlined above, make sure your `build.sbt` contains
     the empty lines; they are required by `sbt`.
 
 [1]: https://www.atlassian.com/blog/git/alternatives-to-git-submodule-git-subtree

axi4.py

+__port_map = {
+	'AWID'     : 'io_{0}_writeAddr_bits_id',
+	'AWADDR'   : 'io_{0}_writeAddr_bits_addr',
+	'AWLEN'    : 'io_{0}_writeAddr_bits_burst_len',
+	'AWSIZE'   : 'io_{0}_writeAddr_bits_burst_size',
+	'AWBURST'  : 'io_{0}_writeAddr_bits_burst_burst',
+	'AWLOCK'   : 'io_{0}_writeAddr_bits_lock_lock',
+	'AWCACHE'  : 'io_{0}_writeAddr_bits_cache_cache',
+	'AWPROT'   : 'io_{0}_writeAddr_bits_prot_prot',
+	'AWQOS'    : 'io_{0}_writeAddr_bits_qos',
+	'AWREGION' : 'io_{0}_writeAddr_bits_region',
+	'AWUSER'   : 'io_{0}_writeAddr_bits_user',
+	'AWVALID'  : 'io_{0}_writeAddr_valid',
+	'AWREADY'  : 'io_{0}_writeAddr_ready',
+	'WID'      : 'io_{0}_writeData_bits_id',
+	'WDATA'    : 'io_{0}_writeData_bits_data',
+	'WSTRB'    : 'io_{0}_writeData_bits_strb_strb',
+	'WLAST'    : 'io_{0}_writeData_bits_last',
+	'WUSER'    : 'io_{0}_writeData_bits_user',
+	'WVALID'   : 'io_{0}_writeData_valid',
+	'WREADY'   : 'io_{0}_writeData_ready',
+	'BID'      : 'io_{0}_writeResp_bits_bid',
+	'BRESP'    : 'io_{0}_writeResp_bits_bresp',
+	'BUSER'    : 'io_{0}_writeResp_bits_buser',
+	'BVALID'   : 'io_{0}_writeResp_valid',
+	'BREADY'   : 'io_{0}_writeResp_ready',
+	'ARID'     : 'io_{0}_readAddr_bits_id',
+	'ARADDR'   : 'io_{0}_readAddr_bits_addr',
+	'ARLEN'    : 'io_{0}_readAddr_bits_burst_len',
+	'ARSIZE'   : 'io_{0}_readAddr_bits_burst_size',
+	'ARBURST'  : 'io_{0}_readAddr_bits_burst_burst',
+	'ARLOCK'   : 'io_{0}_readAddr_bits_lock_lock',
+	'ARCACHE'  : 'io_{0}_readAddr_bits_cache_cache',
+	'ARPROT'   : 'io_{0}_readAddr_bits_prot_prot',
+	'ARQOS'    : 'io_{0}_readAddr_bits_qos',
+	'ARREGION' : 'io_{0}_readAddr_bits_region',
+	'ARUSER'   : 'io_{0}_readAddr_bits_user',
+	'ARVALID'  : 'io_{0}_readAddr_valid',
+	'ARREADY'  : 'io_{0}_readAddr_ready',
+	'RID'      : 'io_{0}_readData_bits_id',
+	'RDATA'    : 'io_{0}_readData_bits_data',
+	'RRESP'    : 'io_{0}_readData_bits_resp',
+	'RLAST'    : 'io_{0}_readData_bits_last',
+	'RUSER'    : 'io_{0}_readData_bits_user',
+	'RVALID'   : 'io_{0}_readData_valid',
+	'RREADY'   : 'io_{0}_readData_ready'
+}
+
+def get_port_dict(name):
+        return {k: v.format(name) for k, v in __port_map.items()}

build.sbt

@@ -2,11 +2,9 @@ name := "chisel-packaging"
 
 organization := "esa.cs.tu-darmstadt.de"
 
-version := "0.2-SNAPSHOT"
+version := "0.3-SNAPSHOT"
 
-scalaVersion := "2.11.0"
-
-crossScalaVersions := Seq("2.10.3", "2.10.4", "2.11.0")
+scalaVersion := "2.11.11"
 
 resolvers ++= Seq(
   Resolver.sonatypeRepo("snapshots"),
@@ -21,6 +19,7 @@ libraryDependencies ++= (Seq("chisel3","chisel-iotesters").map {
   dep: String => "edu.berkeley.cs" %% dep % sys.props.getOrElse(dep + "Version", defaultVersions(dep)) })
 
 libraryDependencies ++= Seq(
-  "com.typesafe.play" %% "play-json" % "2.4.8"
+  "com.typesafe.play" %% "play-json" % "2.6.3"
 )
 
+scalacOptions += "-feature"

package.py

@@ -3,6 +3,7 @@
 import json
 import argparse
 from subprocess import Popen, STDOUT, PIPE
+import axi4
 
 script = '''
 create_project -force "{0}" /tmp
@@ -19,6 +20,84 @@ ipx::save_core [ipx::current_core]
 close_project -delete
 '''
 
+__interface_script = '''
+set name    "{0}"
+set vendor  "{1}"
+set library "{2}"
+set version "{3}"
+set root    "{4}"
+set mainmod "{5}"
+
+cd $root
+
+create_project -in_memory $root
+update_ip_catalog
+ipx::create_core $vendor $library $name $version
+
+set core [ipx::current_core]
+
+set_property supported_families {{virtex7 Production qvirtex7 Production kintex7 Production kintex7l Production qkintex7 Production qkintex7l Production artix7 Production artix7l Production aartix7 Production qartix7 Production zynq Production qzynq Production azynq Production}} $core
+
+#set_property core_revision 1 $core
+set_property display_name $name $core
+set_property description $name $core
+set_property taxonomy $library $core
+
+set fg [ipx::add_file_group -type synthesis "sources" $core]
+set_property -dict [list model_name $name language Verilog] $fg
+ipx::import_top_level_hdl -top_level_hdl_file $mainmod -verbose $core
+
+set clk [ipx::add_bus_interface clock $core]
+set_property type_name std_logic [ipx::add_port "clock" $core]
+set_property -dict [list \
+  abstraction_type_vlnv {{xilinx.com:signal:clock_rtl:1.0}} \
+  bus_type_vlnv {{xilinx.com:signal:clock:1.0}}] $clk
+set_property physical_name "clock" [ipx::add_port_map "CLK" $clk]
+
+set rst [ipx::add_bus_interface reset $core]
+set_property type_name std_logic [ipx::add_port "reset" $core]
+set_property -dict [list \
+  abstraction_type_vlnv {{xilinx.com:signal:reset_rtl:1.0}} \
+  bus_type_vlnv {{xilinx.com:signal:reset:1.0}}] $rst
+set_property value ACTIVE_HIGH [ipx::add_bus_parameter POLARITY $rst]
+set_property physical_name "reset" [ipx::add_port_map "RST" $rst]
+
+{6}
+
+ipx::create_default_gui_files $core
+ipx::update_checksums $core
+ipx::save_core $core
+ipx::archive_core "$root/$name.zip" $core
+#close_project -delete
+'''
+
+__axi4Tcl = '''
+set if [ipx::add_bus_interface "{0}" $core]
+set_property -dict [list \
+  abstraction_type_vlnv {{xilinx.com:interface:axi4mm_rtl:1.0}} \
+  bus_type_vlnv {{xilinx.com:interface:axi4mm:1.0}} \
+  interface_mode {1}] $if
+ipx::associate_bus_interfaces -busif "{0}" -clock clock -reset reset $core
+foreach {{bport port}} {2} {{
+  puts "$bport $port"
+  set_property physical_name "$port" [ipx::add_port_map $bport $if]
+}}
+'''
+
+def map_interface(name, kind):
+	if kind == 'axi4master':
+		script = __axi4Tcl.format(name, 'master', make_tcl_port_list(axi4.get_port_dict(name)))
+		return script
+	elif kind == 'axi4slave':
+		script = __axi4Tcl.format(name, 'slave', make_tcl_port_list(axi4.get_port_dict(name)))
+		return script
+	else:
+		print 'unknown interface: ' + kind
+		return ''
+
+def make_tcl_port_list(d, f=lambda x: x):
+        return "[list " + ' '.join([k + ' ' + f(d[k]) for k in sorted(d.keys())]) + "]"
+
 def read_json(jsonfile):
 	with open(jsonfile, 'r') as jf:
 		contents = jf.read()
@@ -26,7 +105,13 @@ def read_json(jsonfile):
 
 def make_vivado_script(jsonfile):
 	cd = read_json(jsonfile)
-	return script.format(cd['name'], cd['vendor'], cd['library'], cd['version'], cd['root'])
+	if ('interfaces' not in cd) or (len(cd['interfaces']) is 0):
+		#print 'found no interfaces, or empty interface list, using auto-inference'
+		return script.format(cd['name'], cd['vendor'], cd['library'], cd['version'], cd['root'])
+	else:
+		#print 'found interfaces: ', cd['interfaces']
+		ifs = '\n'.join([map_interface(i['name'], i['kind']) for i in cd['interfaces']])
+		return __interface_script.format(cd['name'], cd['vendor'], cd['library'], cd['version'], cd['root'], cd['root'] + '/' + cd['name'] + '.v', ifs)
 
 def run_vivado(script):
 	p = Popen(['vivado', '-mode', 'tcl', '-nolog', '-nojournal'], stdin=PIPE, stdout=PIPE, stderr=STDOUT)
@@ -40,3 +125,4 @@ def parse_args():
 
 args = parse_args()
 run_vivado(make_vivado_script(args.json))
+#print make_vivado_script(args.json)