Bugfix for latest Chisel3

* zero-width io ports must be assigned, or compilation will fail
* fixed RegisterFileSpec accordingly
* updated to Scala 2.11.12

build.sbt

@@ -4,7 +4,7 @@ organization := "esa.cs.tu-darmstadt.de"
 
 version := "0.4-SNAPSHOT"
 
-scalaVersion := "2.11.11"
+scalaVersion := "2.11.12"
 
 resolvers ++= Seq(
   Resolver.sonatypeRepo("snapshots"),

src/test/scala/axi4lite/RegisterFileSpec.scala

@@ -30,6 +30,10 @@ class RegFileTest(val size: Int, val off: Int, regs: Map[Long, ControlRegister],
     val wresp = Irrevocable(new chisel.axi.Axi4Lite.WriteResponse)
     val finished = Output(Bool())
   })
+  m.io.start        := 0.U
+  m.io.restart      := 0.U
+  m.io.out.ready    := true.B
+  m.io.w_resp.ready := true.B
   m.io.maxi         <> saxi.io.saxi
   io.finished       := m.io.finished
   io.wresp          <> saxi.io.saxi.writeResp