Commit a9f329c5 authored by Jens Korinth's avatar Jens Korinth
Browse files

Bugfix for latest Chisel3

* zero-width io ports must be assigned, or compilation will fail
* fixed RegisterFileSpec accordingly
* updated to Scala 2.11.12
parent 8d79675d
...@@ -4,7 +4,7 @@ organization := "esa.cs.tu-darmstadt.de" ...@@ -4,7 +4,7 @@ organization := "esa.cs.tu-darmstadt.de"
version := "0.4-SNAPSHOT" version := "0.4-SNAPSHOT"
scalaVersion := "2.11.11" scalaVersion := "2.11.12"
resolvers ++= Seq( resolvers ++= Seq(
Resolver.sonatypeRepo("snapshots"), Resolver.sonatypeRepo("snapshots"),
......
...@@ -30,6 +30,10 @@ class RegFileTest(val size: Int, val off: Int, regs: Map[Long, ControlRegister], ...@@ -30,6 +30,10 @@ class RegFileTest(val size: Int, val off: Int, regs: Map[Long, ControlRegister],
val wresp = Irrevocable(new chisel.axi.Axi4Lite.WriteResponse) val wresp = Irrevocable(new chisel.axi.Axi4Lite.WriteResponse)
val finished = Output(Bool()) val finished = Output(Bool())
}) })
m.io.start := 0.U
m.io.restart := 0.U
m.io.out.ready := true.B
m.io.w_resp.ready := true.B
m.io.maxi <> saxi.io.saxi m.io.maxi <> saxi.io.saxi
io.finished := m.io.finished io.finished := m.io.finished
io.wresp <> saxi.io.saxi.writeResp io.wresp <> saxi.io.saxi.writeResp
......
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