Commit af11427a authored by Jaco Hofmann's avatar Jaco Hofmann
Browse files

Improve compatability of SumeClockProgrammer

parent 642f59a7
......@@ -81,6 +81,22 @@
</spirit:portMap>
</spirit:portMaps>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>led_clock</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
<spirit:master/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CLK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>led_clock</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
</spirit:busInterface>
</spirit:busInterfaces>
<spirit:model>
<spirit:views>
......@@ -96,7 +112,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>3e5969dd</spirit:value>
<spirit:value>39aaed8a</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
......@@ -112,7 +128,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>3e5969dd</spirit:value>
<spirit:value>39aaed8a</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
......@@ -297,7 +313,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>led</spirit:name>
<spirit:name>led_clock</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
......@@ -309,6 +325,32 @@
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>led_init_done</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>reprogram_do_reprogram</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
</spirit:ports>
</spirit:model>
<spirit:choices>
......@@ -336,7 +378,7 @@
<spirit:file>
<spirit:name>src/mkSumeClockProgrammer.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>CHECKSUM_2beafd7b</spirit:userFileType>
<spirit:userFileType>CHECKSUM_57b9d83e</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
......@@ -404,16 +446,16 @@
<xilinx:displayName>SumeClockProgrammer</xilinx:displayName>
<xilinx:definitionSource>package_project</xilinx:definitionSource>
<xilinx:coreRevision>1</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2018-08-30T11:15:13Z</xilinx:coreCreationDateTime>
<xilinx:coreCreationDateTime>2018-09-18T08:37:22Z</xilinx:coreCreationDateTime>
<xilinx:tags>
<xilinx:tag xilinx:name="nopcore"/>
</xilinx:tags>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2018.1</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="8ed3f42f"/>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="9868e58e"/>
<xilinx:checksum xilinx:scope="ports" xilinx:value="ad567f61"/>
<xilinx:xilinxVersion>2018.2</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="06d0737d"/>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="8f35b6c9"/>
<xilinx:checksum xilinx:scope="ports" xilinx:value="a96ad7b0"/>
<xilinx:checksum xilinx:scope="parameters" xilinx:value="409ff535"/>
</xilinx:packagingInfo>
</spirit:vendorExtensions>
......
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