Commit b8f4c554 authored by Jens Korinth's avatar Jens Korinth
Browse files

Fix bug in Register implementation

* width would not be propagated correctly
* fixed, also changed standard write test to increase by 1 from offset,
  making accidental correctness less likely
parent 886e04b9
......@@ -125,7 +125,7 @@ object RegisterFile {
in_q_wa.io.deq.ready := in_q_wd.io.deq.valid && out_q_wr.io.enq.ready
in_q_wd.io.deq.ready := in_q_wa.io.deq.valid && out_q_wr.io.enq.ready
when (in_q_wa.io.deq.fire) {
when (in_q_wa.io.deq.fire) { // ready/valid handshakes locked with in_q_wd above
val addr = in_q_wa.io.deq.bits
val v = in_q_wd.io.deq.bits
for (off <- cfg.regs.keys.toList.sorted) {
......
......@@ -55,9 +55,9 @@ class ConstantRegister(name: Option[String] = None, bitfield: BitfieldMap = Map(
* @param name Name of the register (optional).
* @param bitfield Bit partitioning of the value (optional).
**/
class Register(name: Option[String] = None, bitfield: BitfieldMap = Map(), width: Int)
class Register(name: Option[String] = None, bitfield: BitfieldMap = Map(), width: Axi4Lite.DataWidth)
extends ControlRegister(name, bitfield) {
private lazy val _r = RegInit(0.U(width))
private lazy val _r = RegInit(0.U(width = width))
def read(): Option[UInt] = Some(_r)
override def write(v: UInt) = {
_r := v
......
......@@ -45,11 +45,11 @@ class RegisterFileSpec extends ChiselFlatSpec with Checkers {
private def generateActionsFromRegMap(regs: Map[Long, Option[ControlRegister]]): Seq[MasterAction] =
regs.toSeq.sortBy(_._1) map { _ match {
case (i, Some(r)) => r match {
case c: Register => Seq(MasterWrite(i, i), MasterRead(i))
case c: Register => Seq(MasterWrite(i, i + 1), MasterRead(i))
case c: ConstantRegister => Seq(MasterRead(i))
case _ => Seq()
}
case (i, None) => Seq(MasterRead(i), MasterWrite(i, i))
case (i, None) => Seq(MasterRead(i), MasterWrite(i, i + 1))
}} reduce (_ ++ _)
private def genericTest(width: DataWidth, regs: Map[Long, Option[ControlRegister]])
......@@ -105,7 +105,7 @@ class RegisterFileSpec extends ChiselFlatSpec with Checkers {
val resp = peek(m.io.rdata.bits.resp)
expect (m.io.rdata.bits.resp, Response.okay, s"[$off] read response is 0x%x (%d), should be 0 (OKAY)".format(resp, resp))
val data = peek(m.io.rdata.bits.data)
expect (m.io.rdata.bits.data, off, s"[$off] read data is 0x%x (%d), should be %d".format(data, data, off))
expect (m.io.rdata.bits.data, off + 1, s"[$off] read data is 0x%x (%d), should be %d".format(data, data, off + 1))
}
def test(r: ConstantRegister, off: Int) {
......
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