Commit b992dd73 authored by Jens Korinth's avatar Jens Korinth
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README.md edited online with Bitbucket

parent f15683a7
......@@ -2,9 +2,15 @@ Chisel IP-XACT packaging for Xilinx Vivado Design Suite
=======================================================
Helper scripts and Scala classes to simplify the generation of IP-XACT IP cores from Chisel.
Uses *Xilinx Vivado Design Suite* [[2]] to infer most of the interfaces automatically.
Resulting `component.xml` can be edited manually or with Vivado, if the automagic did not
fit your needs.
Uses [*Xilinx Vivado Design Suite*] [2] to infer most of the interfaces automatically.
The resulting `component.xml` files can be edited manually or with Vivado, if the automagic
did not fit your needs.
Requirements
----------------------
* Vivado 2016.x+
* Chisel 3.x *(currently using `3.0-SNAPSHOT`)*
* *optional*: sbt
Basic Usage
-----------
......@@ -13,50 +19,49 @@ method. You'll only need to provide a list of Chisel cores you'd like to wrap in
A full example can be found in `examples`; test it as follows:
1. Source the Vivado settings scripts, make sure `vivado` is in the `PATH`.
2. In the `chisel-packaging` base dir, do:
```
cp examples/* .
```
2. In the `chisel-packaging` base dir, do:
cp examples/* .
3. Execute via:
```
sbt run
```
sbt run
4. This should create a new directory `ip`, which contains subdirectories for each core.
The subdirectories contain the Verilog sources and the IP-XACT `component.xml`.
You can use the `ip` directory as a base directory for user IP in Vivado, the cores should
automatically appear in Vivado and IP-Integrator.
to run it, copy it to the project main directory
and simply run `sbt run`. This will produce a new subdirectory `ip`, which contains further
subdirectories for each core. You can use this directory as a repository base in Xilinx
Vivado Design Suite, the cores can then be used in Vivado projects and IP integrator.
Usage in Chisel Projects (*sbt*)
--------------------------------
The easiest way to setup `chisel-packaging` for your Chisel project w/`sbt` project is using
**git subtree** (see [[1]] for an excellent intro to subtrees) as follows:
The easiest way to setup `chisel-packaging` for your Chisel project with `sbt` is using
**git subtree** ([this article] [1] has an excellent intro to subtrees) as follows:
1. In your the base directory of your project, add a new remote *chisel-packaging*:
```
git remote add chisel-packaging https://bitbucket.org/jkorinth/chisel-packaging.git
```
git remote add chisel-packaging https://bitbucket.org/jkorinth/chisel-packaging.git
2. Setup a subtree in `packaging`:
```
git subtree add --prefix packaging chisel-packaging master --squash
```
This will clone the `chisel-packaging` into the `packaging` folder.
git subtree add --prefix packaging chisel-packaging master --squash
This will clone the `chisel-packaging` into the `packaging` folder.
3. Add a project dependency in your `build.sbt`, add lines:
```
lazy val packaging = project.in(file("packaging"))
lazy val root = (project in file(".")).dependsOn(packaging)
```
*Note that the empty lines are **not optional** - a quirk of sbt.*
lazy val packaging = project.in(file("packaging"))
lazy val root = (project in file(".")).dependsOn(packaging)
*Note that the empty lines are **not optional** - a quirk of sbt.*
4. Implement `chisel.packaging.ModuleBuilder` in your own code; if you've chosen
a different directory than `packaging` for the subtree, you can pass it to the
baseclass constructor -- see [examples/ModuleBuilder.scala].
baseclass constructor -- see [examples/ModuleBuilder.scala](examples/ModuleBuilder.scala).
5. Build the IP-XACT cores via `sbt run`.
Gotchas
......
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