Commit bd890015 authored by Jens Korinth's avatar Jens Korinth
Browse files

WIP: remove Bundle interfaces, does not work :-(

* will need to use individual pins
* started to move subsystem code to subsystem.tcl
parent 3cdff64a
Pipeline #83 passed with stage
in 3 minutes and 3 seconds
......@@ -21,6 +21,9 @@
# @authors J. Korinth, TU Darmstadt (jk@esa.cs.tu-darmstadt.de)
#
namespace eval tapasco {
if {[info commands version] != ""} \
{ source -notrace $::env(TAPASCO_HOME)/common/subsystem.tcl } \
{ source $::env(TAPASCO_HOME)/common/subsystem.tcl }
namespace export createBinaryCounter
namespace export createClockingWizard
namespace export createConcat
......
#
# Copyright (C) 2017 Jens Korinth, TU Darmstadt
#
# This file is part of Tapasco (TPC).
#
# Tapasco is free software: you can redistribute it and/or modify
# it under the terms of the GNU Lesser General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# Tapasco is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU Lesser General Public License for more details.
#
# You should have received a copy of the GNU Lesser General Public License
# along with Tapasco. If not, see <http://www.gnu.org/licenses/>.
#
# @file subsystem.tcl
# @brief Subsystem block creation helpers.
# @author J. Korinth, TU Darmstadt (jk@esa.tu-darmstadt.de)
#
namespace eval subsystem {
namespace export create
namespace export get_port
# Creates a hierarchical cell with given name and interface ports for clocks
# and resets of the three base clocks in TaPaSCo designs.
# @param is_source if true, will create output ports, otherwise input ports
proc create {name {is_source false} {prefix ""}} {
set instance [current_bd_instance]
set cell [create_bd_cell -type hier $name]
set intf_vlnv [tapasco::get_vlnv "tapasco_clocks_resets"]
current_bd_instance $cell
set d [expr "{$is_source} ? {O} : {I}"]
foreach c {host design mem} {
puts " creating $c connections ..."
set clk [create_bd_pin -type clk -dir $d "${prefix}${c}_clk"]
set prstn [create_bd_pin -type rst -dir $d "${prefix}${c}_peripheral_aresetn"]
set prst [create_bd_pin -type rst -dir $d "${prefix}${c}_peripheral_areset"]
set irstn [create_bd_pin -type rst -dir $d "${prefix}${c}_interconnect_aresetn"]
set_property CONFIG.POLARITY ACTIVE_LOW $prstn $irstn
}
current_bd_instance $instance
return $cell
}
proc get_ports {} {
set d [dict create]
foreach c {host design mem} {
set clk [get_bd_pins -of_objects [current_bd_instance .] -filter "NAME == ${c}_clk && TYPE == clk"]
set prstn [get_bd_pins -of_objects [current_bd_instance .] -filter "NAME == ${c}_peripheral_aresetn && TYPE == rst"]
set prst [get_bd_pins -of_objects [current_bd_instance .] -filter "NAME == ${c}_peripheral_areset && TYPE == rst"]
set irstn [get_bd_pins -of_objects [current_bd_instance .] -filter "NAME == ${c}_interconnect_aresetn && TYPE == rst"]
dict set d $c "clk" $clk
dict set d $c "rst" "peripheral" "resetn" $prstn
dict set d $c "rst" "peripheral" "reset" $prst
dict set d $c "rst" "interconnect" "resetn" $irstn
}
return $d
}
# Returns pin of given type on the sub-block interface of the current instance.
proc get_port {args} {
if {[catch {dict get [get_ports] {*}$args} err]} {
puts "ERROR: $err"
error "get_port: invalid args $args"
}
set r [dict get [get_ports] {*}$args]
if {[llength $r] == 0 || [llength $r] > 1} {
if {[catch {error "get_port: incomplete args $args: $r"} err]} {
puts "ERROR: $::errorInfo"
}
}
return $r
}
}
......@@ -33,11 +33,11 @@ namespace eval platform {
proc create {} {
set instance [current_bd_instance]
# create mandatory subsystems
set ss_host [create_subsystem "host"]
set ss_cnrs [create_subsystem "clocks_and_resets" false true]
set ss_mem [create_subsystem "memory"]
set ss_intc [create_subsystem "intc"]
set ss_tapasco [create_subsystem "tapasco"]
set ss_host [tapasco::subsystem::create "host"]
set ss_cnrs [tapasco::subsystem::create "clocks_and_resets" false true]
set ss_mem [tapasco::subsystem::create "memory"]
set ss_intc [tapasco::subsystem::create "intc"]
set ss_tapasco [tapasco::subsystem::create "tapasco"]
set sss [list $ss_cnrs $ss_host $ss_intc $ss_mem $ss_tapasco]
......@@ -65,7 +65,7 @@ namespace eval platform {
foreach ss [info commands create_custom_subsystem_*] {
set name [regsub {.*create_custom_subsystem_(.*)} $ss {\1}]
puts "Creating custom subsystem $name ..."
current_bd_instance [create_subsystem $name]
current_bd_instance [tapasco::subsystem::create $name]
eval $ss
current_bd_instance $instance
}
......@@ -74,49 +74,6 @@ namespace eval platform {
wire_subsystem_intfs
}
# Creates a hierarchical cell with given name and instantiates either a
# ClocksResetsBridgeMaster or ClocksResetsBridgeSlave, depending on whether
# is_reset is true or false, respectively. get_clock_reset_port can be used
# to access the pins in this component.
proc create_subsystem {name {has_slave true} {has_master true}} {
set instance [current_bd_instance]
set cell [create_bd_cell -type hier $name]
set intf_vlnv [tapasco::get_vlnv "tapasco_clocks_resets"]
current_bd_instance $cell
if {$has_master} {
set m_port [create_bd_intf_pin -vlnv $intf_vlnv -mode Master "M_CLOCKS_RESETS"]
set m_cnrs [create_bd_cell -type ip -vlnv [tapasco::get_vlnv "clocks_resets_m"] "m_cnrs"]
connect_bd_intf_net [get_bd_intf_pins -of_objects $m_cnrs -filter "VLNV == $intf_vlnv"] $m_port
}
if {$has_slave} {
set s_port [create_bd_intf_pin -vlnv $intf_vlnv -mode Slave "S_CLOCKS_RESETS"]
set s_cnrs [create_bd_cell -type ip -vlnv [tapasco::get_vlnv "clocks_resets_s"] "s_cnrs"]
connect_bd_intf_net $s_port [get_bd_intf_pins -of_objects $s_cnrs -filter "VLNV == $intf_vlnv"]
}
if {$has_master && $has_slave} {
# directly connect all wires
foreach p [get_bd_pins -of_objects $m_cnrs -filter { NAME =~ i_* }] {
set oname [regsub {i_} [get_property NAME $p] {o_}]
set op [get_bd_pins -of_objects $s_cnrs -filter "NAME == $oname"]
puts " connecting $p to $op ..."
connect_bd_net $p $op
}
}
current_bd_instance $instance
return $cell
}
# Returns pin with given name on the clocks and resets bridge component in
# the current subsystem.
proc get_clock_reset_port {name} {
set cells [get_bd_cells -filter "VLNV == [tapasco::get_vlnv clocks_resets_s] || VLNV == [tapasco::get_vlnv clocks_resets_m]"]
return [get_bd_pins -of_objects $cells -filter "NAME == $name && INTF == false"]
}
proc get_pe_base_address {} {
error "Platform does not implement mandatory proc get_pe_base_address!"
}
......@@ -125,8 +82,8 @@ namespace eval platform {
set port [create_bd_intf_pin -vlnv [tapasco::get_vlnv "aximm_intf"] -mode Slave "S_TAPASCO"]
set tapasco_status [tapasco::createTapascoStatus "tapasco_status"]
connect_bd_intf_net $port [get_bd_intf_pins -of_objects $tapasco_status -filter "VLNV == [tapasco::get_vlnv aximm_intf] && MODE == Slave"]
connect_bd_net [get_clock_reset_port "o_design_clk"] [get_bd_pins -of_objects $tapasco_status -filter {TYPE == clk && DIR == I}]
connect_bd_net [get_clock_reset_port "o_design_peripheral_reset"] [get_bd_pins -of_objects $tapasco_status -filter {TYPE == rst && DIR == I}]
connect_bd_net [tapasco::subsystem::get_port "design" "clk"] [get_bd_pins -of_objects $tapasco_status -filter {TYPE == clk && DIR == I}]
connect_bd_net [tapasco::subsystem::get_port "design" "peripheral" "rst" false] [get_bd_pins -of_objects $tapasco_status -filter {TYPE == rst && DIR == I}]
}
proc wire_subsystem_wires {} {
......
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