Commit bea8ec99 authored by Jens Korinth's avatar Jens Korinth
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README.md

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TaPaSCo Status Core
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Starting from version 1.2, the TaPaSCo status IP core will be built from Chisel.
Maintaining the growing demand for new registers, different kinds of information
etc. made it unwieldy to use Verilog IP. Instead, a custom IP core is generated
for each composition.
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