Commit beb71c3d authored by Jens Korinth's avatar Jens Korinth
Browse files

Rebuild all Platforms using new skeleton

* rebuilt PyNQ, zedboard and ZC706 without features
* expanded subsystem package: standard and custom subsystems can be
  fetched (as bd cells) and their names queried (incl. custom)
* Zynqs adapt the memory system to bypass
* need to run more tests, but looks good
* timing problems in VC709, need to investigate
parent 6cb43d23
......@@ -40,7 +40,7 @@ namespace eval arch {
# Returns a list of the bd_cells of slave interfaces of the threadpool.
proc get_slaves {} {
set inst [current_bd_instance]
current_bd_instance "/uArch"
current_bd_instance [::tapasco::subsystem::get arch]
set r [list [get_bd_intf_pins -of [get_bd_cells "in1"] -filter { MODE == "Slave" }]]
current_bd_instance $inst
return $r
......@@ -53,12 +53,12 @@ namespace eval arch {
}
proc get_processing_elements {} {
return [get_bd_cells "/uArch/target*"]
return [get_bd_cells -of_objects [::tapasco::subsystem::get arch] -filter { NAME =~ target*}]
}
# Returns a list of interrupt lines from the threadpool.
proc get_irqs {} {
return [get_bd_pins -of_objects [get_bd_cells "uArch"] -filter {TYPE == "intr" && DIR == "O"}]
return [get_bd_pins -of_objects [::tapasco::subsystem::get arch] -filter {TYPE == "intr" && DIR == "O"}]
}
# Checks, if the current composition can be instantiated. Exits script with
......@@ -339,7 +339,7 @@ namespace eval arch {
foreach irq_concat $arch_irq_concats {
# create hierarchical port with correct width
set port [get_bd_pins -of_objects $irq_concat -filter {DIR == "O"}]
set out_port [create_bd_pin -type INTR -dir O -from [get_property LEFT $port] -to [get_property RIGHT $port] "irq_$i"]
set out_port [create_bd_pin -type INTR -dir O -from [get_property LEFT $port] -to [get_property RIGHT $port] "intr_$i"]
connect_bd_net $port $out_port
incr i
}
......@@ -374,7 +374,7 @@ namespace eval arch {
}
# create hierarchical group
set group [tapasco::subsystem::create "uArch"]
set group [tapasco::subsystem::create "arch"]
set instance [current_bd_instance .]
current_bd_instance $group
......
......@@ -29,11 +29,11 @@ namespace eval arch {
set masters [lsort [tapasco::get_aximm_interfaces $pe]]
foreach intf $masters {
set space [get_bd_addr_spaces -of_objects $intf]
set offset [get_property OFFSET $space]
if {$offset == ""} { set offset 0 }
set off [get_property OFFSET $space]
if {$off == ""} { set off 0 }
set range [get_property RANGE $space]
if {$range == ""} { error "no range found on $space for $intf!" }
dict set ret $intf "interface $intf [format "offset 0x%08x range 0x%08x" $offset $range] kind master"
dict set ret $intf "interface $intf [format "offset 0x%08x range 0x%08x" $off $range] kind master"
}
}
return $ret
......
......@@ -287,7 +287,7 @@ namespace eval tapasco {
for {set i 0} {$i < $n} {incr i} {
set rest_ports [expr "$nports - $i * 16"]
set rest_ports [expr "min($rest_ports, 16)"]
set nic [::tapasco:ip::create_axi_ic [format "ic_%03d" $ic_n] [expr "$masters ? $rest_ports : 1"] [expr "$masters ? 1 : $rest_ports"]]
set nic [ip::create_axi_ic [format "ic_%03d" $ic_n] [expr "$masters ? $rest_ports : 1"] [expr "$masters ? 1 : $rest_ports"]]
incr ic_n
lappend curr_ics $nic
}
......@@ -374,94 +374,6 @@ namespace eval tapasco {
return $group
}
# Creates a subsystem with clock and reset generation for a list of clocks.
# Consists of clocking wizard + reset generators with single ext. reset in.
# @param freqs list of name frequency (MHz) pairs, e.g., [list design 100 memory 250]
# @param name Name of the subsystem group
# @return Subsystem group
proc create_subsystem_clocks_and_resets {{freqs {}} {name ClockResets}} {
if {$freqs == {}} { set freqs [get_frequencies] }
puts "Creating clock and reset subsystem ..."
puts " frequencies: $freqs"
set instance [current_bd_instance .]
set group [create_bd_cell -type hier $name]
current_bd_instance $group
set reset_in [create_bd_pin -dir I -type rst "reset_in"]
set clk [createClockingWizard "clk_wiz"]
set_property -dict [list CONFIG.USE_LOCKED {false} CONFIG.USE_RESET {false} CONFIG.NUM_OUT_CLKS [expr "[llength $freqs] / 2"]] $clk
set clk_mode "sys_diff_clock"
if {[catch {set_property CONFIG.CLK_IN1_BOARD_INTERFACE {sys_diff_clock} $clk}]} {
puts " sys_diff_clock is not supported, trying sys_clock instead"
set clk_mode "sys_clock"
}
# check if external port already exists, re-use
if {[catch [get_bd_ports "/$clk_mode"]]} {
# connect existing top-level port
connect_bd_net [get_bd_ports "/$clk_mode"] [get_bd_pins -filter {TYPE == clk && DIR == I} -of_objects $clk]
# use PLL primitive for all but the first subsystem (MMCMs are limited)
set_property -dict [list CONFIG.PRIMITIVE {PLL} CONFIG.USE_MIN_POWER {true}] $clk
} {
# apply board automation to create top-level port
if {$clk_mode == "sys_diff_clock"} {
set cport [get_bd_intf_pins -of_objects $clk]
} {
set cport [get_bd_pins -filter {DIR == I} -of_objects $clk]
}
puts " clk: $clk, cport: $cport"
if {$cport != {}} {
# apply board automation
apply_bd_automation -rule xilinx.com:bd_rule:board -config "Board_Interface $clk_mode" $cport
puts "board automation worked, moving on"
} {
# last resort: try to call platform::create_clock_port
set clk_mode "sys_clk"
set cport [platform::create_clock_port $clk_mode]
connect_bd_net $cport [get_bd_pins -filter {TYPE == clk && DIR == I} -of_objects $clk]
}
}
for {set i 0; set clkn 1} {$i < [llength $freqs]} {incr i 2} {
set name [lindex $freqs $i]
set freq [lindex $freqs [expr $i + 1]]
#set clkn [expr "$i / 2 + 1"]
puts " instantiating clock: $name @ $freq MHz"
for {set j 0} {$j < $i} {incr j 2} {
if {[lindex $freqs [expr $j + 1]] == $freq} {
puts " $name is same frequency as [lindex $freqs $j], re-using"
break
}
}
# create ports
set port [create_bd_pin -dir O -type clk ${name}_aclk]
set p_rst [create_bd_pin -dir O -type rst "${name}_peripheral_aresetn"]
set i_rst [create_bd_pin -dir O -type rst "${name}_interconnect_aresetn"]
if {[expr "$j < $i"]} {
# simply re-wire sources
foreach p [list "aclk" "interconnect_aresetn" "peripheral_aresetn"] dst [list $port $i_rst $p_rst] {
puts " j = $j, [lindex $freqs $j]_${p}"
set src [get_bd_pins -filter {DIR == O} -of_objects [get_bd_nets -boundary_type lower -of_objects [get_bd_pins "[lindex $freqs $j]_${p}"]]]
connect_bd_net $src $dst
}
} {
set_property -dict [list CONFIG.CLKOUT${clkn}_USED {true} CONFIG.CLKOUT${clkn}_REQUESTED_OUT_FREQ $freq] $clk
set clkp [get_bd_pins "$clk/clk_out${clkn}"]
set rstgen [createResetGen "${name}_rst_gen"]
connect_bd_net $clkp $port
connect_bd_net $reset_in [get_bd_pins "$rstgen/ext_reset_in"]
connect_bd_net $clkp [get_bd_pins "$rstgen/slowest_sync_clk"]
connect_bd_net [get_bd_pins "$rstgen/peripheral_aresetn"] $p_rst
connect_bd_net [get_bd_pins "$rstgen/interconnect_aresetn"] $i_rst
incr clkn
}
}
current_bd_instance $instance
return $group
}
set plugins [dict create]
proc register_plugin {call when} {
......
......@@ -64,8 +64,11 @@ namespace eval ::tapasco::ip {
set irqc [create_bd_cell -type ip -vlnv [dict get $stdcomps axi_irqc vlnv] $name]
# activate edge-sensitive interrupts
set_property -dict [list CONFIG.C_KIND_OF_INTR.VALUE_SRC USER] $irqc
set_property -dict [list CONFIG.C_KIND_OF_INTR {0xFFFFFFFF}] $irqc
set_property -dict [list \
CONFIG.C_KIND_OF_INTR.VALUE_SRC USER \
CONFIG.C_KIND_OF_INTR {0xFFFFFFFF} \
CONFIG.C_IRQ_CONNECTION {1} \
] $irqc
# set_property -dict [list CONFIG.C_EN_CASCADE_MODE {1} CONFIG.C_CASCADE_MASTER {1}] $irqc
return $irqc
}
......
......@@ -24,6 +24,10 @@ namespace eval subsystem {
namespace export create
namespace export get_port
namespace export get_ports
namespace export get_names
namespace export get_custom_names
namespace export get_all
namespace export get
# Creates a hierarchical cell with given name and interface ports for clocks
# and resets of the three base clocks in TaPaSCo designs.
......@@ -74,4 +78,34 @@ namespace eval subsystem {
}
return $r
}
# Returns the names of custom subsystems on this Platform.
proc get_custom {} {
set names [list]
foreach n [info commands ::platform::create_custom_subsystem_*] {
lappend names [regsub {.*create_custom_subsystem_(.*)} $n {\1}]
}
return $names
}
proc get_names {} {
set names [list "arch"]
foreach n [info commands ::platform::create_subsystem_*] {
set name [regsub {.*create_subsystem_(.*)} $n {\1}]
lappend names $name
}
return [concat $names [get_custom]]
}
proc get_all {} {
set cells [dict create]
foreach name [get_names] { dict set cells $name [get_bd_cells "/$name"] }
return $cells
}
proc get {name} {
set all [get_all]
if {![dict exists $all $name]} { error "subsystem $name does not exist!" }
return [dict get [get_all] $name]
}
}
......@@ -203,23 +203,7 @@ namespace eval platform {
}
proc get_address_map {{pe_base ""}} {
set max64 [expr "1 << 64"]
if {$pe_base == ""} { set pe_base [get_pe_base_address] }
set peam [::arch::get_address_map $pe_base]
puts "Computing addresses for masters ..."
foreach m [tapasco::get_aximm_interfaces [get_bd_cells -filter {PATH !~ /uArch/*}]] {
switch -glob [get_property NAME $m] {
"M_DMA" { foreach {base stride range} [list 0x00300000 0x10000 0 ] {} }
"M_INTC" { foreach {base stride range} [list 0x00400000 0x10000 0 ] {} }
"M_MSIX" { foreach {base stride range} [list 0x00500000 0x10000 $max64] {} }
"M_TAPASCO" { foreach {base stride range} [list 0x02800000 0 0 ] {} }
"M_HOST" { foreach {base stride range} [list 0 0 $max64] {} }
"M_ARCH" { set base "skip" }
default { foreach {base stride range} [list 0 0 0] {} }
}
if {$base != "skip"} { set peam [assign_address $peam $m $base $stride $range] }
}
return $peam
error "Platform does not implement mandatory proc get_address_map!"
}
proc assign_address {address_map master base {stride 0} {range 0}} {
......
......@@ -21,7 +21,12 @@
# @author J. Korinth, TU Darmstadt (jk@esa.cs.tu-darmstadt.de)
#
namespace eval leds {
set default_led_pins [list "/uArch/irq_0" "/InterruptControl/irq_out"]
proc default_led_pins {} {
return [concat \
[get_bd_pins -of_objects [::tapasco::subsystem::get arch] -filter { TYPE == intr && DIR == O }] \
[get_bd_pins -of_objects [::tapasco::subsystem::get intc] -filter { TYPE == intr && DIR == O }] \
]
}
proc get_width {input} {
set l [get_property LEFT $input]
......@@ -78,10 +83,9 @@ namespace eval leds {
}
proc create_led_core {{name "gp_led"} {inputs [list]}} {
variable default_led_pins
puts "Creating LED core ..."
if {[llength $inputs] == 0} {
set inputs $default_led_pins
set inputs [default_led_pins]
}
set old_inst [current_bd_instance .]
set cell [create_bd_cell -type hier "LEDs"]
......@@ -109,7 +113,6 @@ namespace eval leds {
proc create_leds {{name "gp_leds"}} {
variable default_led_pins
if {[tapasco::is_feature_enabled "LED"]} {
puts "Implementing Platform feature LED ..."
# create and connect LED core
......
......@@ -19,29 +19,11 @@
source -notrace $::env(TAPASCO_HOME)/platform/zynq/zynq.tcl
namespace eval platform {
namespace export create
namespace export max_masters
namespace export get_address_map
namespace export create_clock_port
namespace export createZynqPS
foreach f [glob -nocomplain -directory "$::env(TAPASCO_HOME)/platform/pynq/plugins" "*.tcl"] {
puts "Found plugin: $f"
source -notrace $f
}
proc max_masters {} {
return [zynq::max_masters]
}
proc get_address_map {} {
return [zynq::get_address_map]
}
proc create {} {
return [zynq::create]
}
proc create_clock_port {{name "sys_clk"}} {
puts "creating 125 MHz clock port ..."
set clk [create_bd_port -dir I -type clk $name]
......@@ -50,15 +32,15 @@ namespace eval platform {
}
}
namespace eval tapasco {
namespace eval ::tapasco::ip {
# overwrite standard procedure
proc createZynqPS {{name ps7} {preset [tapasco::get_board_preset]} {freq_mhz [tapasco::get_design_frequency]}} {
proc create_ps {{name ps7} {preset [tapasco::get_board_preset]} {freq_mhz [tapasco::get_design_frequency]}} {
variable stdcomps
puts "Creating Zynq-7000 series IP core for PyNQ..."
puts " VLNV: [dict get $stdcomps ps vlnv]"
puts " FCLK0 : $freq_mhz"
set ps [create_bd_cell -type ip -vlnv [dict get $stdcomps ps vlnv] $name]
set ps [create_bd_cell -type ip -vlnv [get_vlnv ps] $name]
set_property -dict [ list \
CONFIG.PCW_DDR_RAM_BASEADDR {0x00100000} \
CONFIG.PCW_DDR_RAM_HIGHADDR {0x1FFFFFFF} \
......
......@@ -74,7 +74,7 @@ namespace eval leds {
set inst [create_bd_cell -type ip -vlnv $vlnv $name]
set port [create_bd_port -from 7 -to 0 -dir "O" "LED_Port"]
connect_bd_net [get_bd_pins $inst/LED_Port] $port
read_xdc "$::env(TAPASCO_HOME)/common/ip/GP_LED_1.0/gp_led.xdc"
read_xdc -unmanaged "$::env(TAPASCO_HOME)/common/ip/GP_LED_1.0/gp_led.xdc"
# connect the inputs
for {set i 0} {$i < 6 && [llength $inputs] > $i} {incr i} {
......
namespace eval msix_intr_ctrl {
proc simplify_routing {} {
read_xdc "$::env(TAPASCO_HOME)/common/ip/MSIXIntrCtrl/msix_intr_ctrl.xdc"
read_xdc -unmanaged "$::env(TAPASCO_HOME)/common/ip/MSIXIntrCtrl/msix_intr_ctrl.xdc"
}
}
......
......@@ -39,6 +39,26 @@ namespace eval platform {
return [list 128]
}
proc get_address_map {{pe_base ""}} {
set max64 [expr "1 << 64"]
if {$pe_base == ""} { set pe_base [get_pe_base_address] }
set peam [::arch::get_address_map $pe_base]
puts "Computing addresses for masters ..."
foreach m [::tapasco::get_aximm_interfaces [get_bd_cells -filter "PATH !~ [::tapasco::subsystem::get arch]/*"]] {
switch -glob [get_property NAME $m] {
"M_DMA" { foreach {base stride range} [list 0x00300000 0x10000 0 ] {} }
"M_INTC" { foreach {base stride range} [list 0x00400000 0x10000 0 ] {} }
"M_MSIX" { foreach {base stride range} [list 0x00500000 0x10000 $max64] {} }
"M_TAPASCO" { foreach {base stride range} [list 0x02800000 0 0 ] {} }
"M_HOST" { foreach {base stride range} [list 0 0 $max64] {} }
"M_ARCH" { set base "skip" }
default { foreach {base stride range} [list 0 0 0] {} }
}
if {$base != "skip"} { set peam [assign_address $peam $m $base $stride $range] }
}
return $peam
}
# Setup the clock network.
proc platform_connect_clock {clock_pin} {
puts "Connecting clocks ..."
......@@ -81,13 +101,6 @@ namespace eval platform {
set msix_intr_ctrl [tapasco::ip::create_msix_intr_ctrl "msix_intr_ctrl"]
connect_bd_net [get_bd_pin -of_objects $irq_concat_ss -filter {NAME == "dout"}] [get_bd_pin -of_objects $msix_intr_ctrl -filter {NAME == "interrupt"}]
set curr_pcie_line 4
# connect interrupts to interrupt controller
foreach irq $irqs {
connect_bd_net -boundary_type upper $irq [get_bd_pins -of $irq_concat_ss -filter "NAME == [format "In%d" $curr_pcie_line]"]
incr curr_pcie_line 1
}
connect_bd_intf_net [get_bd_intf_pins -of_objects $msix_intr_ctrl -filter {NAME == "M_AXI"}] $m_axi
connect_bd_net [get_bd_pin -of_objects $msix_intr_ctrl -filter {NAME == "cfg_interrupt_msix_address"}] $msix_addr
connect_bd_net [get_bd_pin -of_objects $msix_intr_ctrl -filter {NAME == "cfg_interrupt_msix_data"}] $msix_data
......@@ -457,229 +470,10 @@ namespace eval platform {
return $axi_pcie3_0
}
proc platform_create_dma_engine {{name "dma_engine"}} {
puts "Creating DMA engine submodule ..."
set inst [current_bd_instance]
set engine [create_bd_cell -type hier dma_engine]
current_bd_instance $engine
set dual_dma_0 [tapasco::ip::create_dualdma dual_dma_0]
current_bd_instance $inst
}
proc get_pe_base_address {} {
return 0x02000000
}
proc platform_address_map_set {{tapasco_base 0x0}} {
# connect AXI slaves
set master_addr_space [get_bd_addr_spaces "/PCIe/axi_pcie3_0/M_AXI"]
# connect DMA controllers
set dmas [lsort [get_bd_addr_segs -of_objects [get_bd_cells "/Memory/dual_dma*"]]]
set offset [expr "$tapasco_base + 0x00300000"]
for {set i 0} {$i < [llength $dmas]} {incr i; incr offset 0x10000} {
create_bd_addr_seg -range 64K -offset $offset $master_addr_space [lindex $dmas $i] "DMA_SEG$i"
}
# connect interrupt controllers
set intcs [lsort [get_bd_addr_segs -of_objects [get_bd_cells /InterruptControl/axi_intc_0*]]]
set offset [expr "$tapasco_base + 0x00400000"]
for {set i 0} {$i < [llength $intcs]} {incr i; incr offset 0x10000} {
create_bd_addr_seg -range 64K -offset $offset $master_addr_space [lindex $intcs $i] "INTC_SEG$i"
}
set msix [get_bd_addr_segs -of_objects [get_bd_cells /InterruptControl/msix_intr_ctrl]]
set offset [expr "$tapasco_base + 0x00500000"]
create_bd_addr_seg -range 64K -offset $offset $master_addr_space $msix "MSIX_SEG"
# connect TPC status core
set status_segs [get_bd_addr_segs -of_objects [get_bd_cells "tapasco_status"]]
set offset [expr "$tapasco_base + 0x02800000"]
set i 0
foreach s $status_segs {
create_bd_addr_seg -range 4K -offset $offset $master_addr_space $s "STATUS_SEG$i"
incr i
incr offset 0x1000
}
# connect user IP
set usrs [lsort [get_bd_addr_segs "/uArch/*"]]
set offset [expr "$tapasco_base + 0x02000000"]
for {set i 0} {$i < [llength $usrs]} {incr i; incr offset 0x10000} {
create_bd_addr_seg -range 64K -offset $offset $master_addr_space [lindex $usrs $i] "USR_SEG$i"
}
# connect AXI masters
foreach dma [lsort [get_bd_cells "/Memory/dual_dma*"]] {
# connect DMA masters
set ms [get_bd_addr_spaces $dma/M64_AXI]
set ts [get_bd_addr_segs /PCIe/axi_pcie3_0/S_AXI/BAR0]
create_bd_addr_seg -range 16E -offset 0 $ms $ts "SEG_$ms"
set ms [get_bd_addr_spaces $dma/M32_AXI]
set ts [get_bd_addr_segs /Memory/mig/*]
create_bd_addr_seg -range 4G -offset 0 $ms $ts "SEG_$ms"
}
set int_ms [get_bd_addr_spaces /InterruptControl/msix_intr_ctrl/M_AXI]
set ts [get_bd_addr_segs /PCIe/axi_pcie3_0/S_AXI/BAR0]
create_bd_addr_seg -range 16E -offset 0 $int_ms $ts "SEG_intr"
# connect user IP
set usrs [lsort [get_bd_addr_spaces /uArch/* -filter { NAME =~ "*m_axi*" || NAME =~ "*M_AXI*" }]]
set ts [get_bd_addr_segs /Memory/mig/*]
foreach u $usrs {
create_bd_addr_seg -range [get_property RANGE $u] -offset 0 $u $ts "SEG_$u"
}
}
proc platform_address_map {} {
platform_address_map_set
# call plugins
tapasco::call_plugins "post-address-map"
}
# Platform API: Entry point for Platform instantiation.
proc createdd {} {
# create interrupt subsystem
set ss_int [create_subsystem_intc [arch::get_irqs]]
# create memory subsystem
set ss_mem [create_subsystem_memory]
# create PCIe subsystem
set ss_pcie [create_subsystem_host]
# create Reset subsystem
set ss_reset [create_subsystem_reset]
# create AXI infrastructure
set axi_ic_to_host [tapasco::ip::create_axi_ic "axi_ic_to_host" 2 1]
set axi_ic_from_host [tapasco::ip::create_axi_ic "axi_ic_from_host" 1 4]
set axi_ic_to_mem [list]
if {[llength [arch::get_masters]] > 0} {
set axi_ic_to_mem [tapasco::ip::create_axi_ic "axi_ic_to_mem" [llength [arch::get_masters]] 1]
connect_bd_intf_net [get_bd_intf_pins $axi_ic_to_mem/M00_AXI] [get_bd_intf_pins /Memory/s_axi_mem]
}
set s_n 0
foreach m [arch::get_masters] {
connect_bd_intf_net $m [get_bd_intf_pins [format "$axi_ic_to_mem/S%02d_AXI" $s_n]]
incr s_n
}
# always create TPC status core
set tapasco_status [tapasco::ip::create_tapasco_status "tapasco_status"]
connect_bd_intf_net [get_bd_intf_pins $axi_ic_from_host/M03_AXI] [get_bd_intf_pins $tapasco_status/S00_AXI]
# connect PCIe <-> InterruptControl
connect_bd_net [get_bd_pins $ss_pcie/msix_fail] [get_bd_pins $ss_int/msix_fail]
connect_bd_net [get_bd_pins $ss_pcie/msix_sent] [get_bd_pins $ss_int/msix_sent]
connect_bd_net [get_bd_pins $ss_pcie/msix_mask] [get_bd_pins $ss_int/msix_mask]
connect_bd_net [get_bd_pins $ss_pcie/msix_enable] [get_bd_pins $ss_int/msix_enable]
connect_bd_net [get_bd_pins $ss_int/msix_data] [get_bd_pins $ss_pcie/msix_data]
connect_bd_net [get_bd_pins $ss_int/msix_addr] [get_bd_pins $ss_pcie/msix_addr]
connect_bd_net [get_bd_pins $ss_int/msix_int] [get_bd_pins $ss_pcie/msix_int]
# connect Memory <-> InterruptControl
connect_bd_net [get_bd_pins $ss_mem/dma_irq] [get_bd_pins $ss_int/dma_irq]
# connect clocks
set pcie_aclk [get_bd_pins $ss_pcie/pcie_aclk]
set ddr_clk [get_bd_pins $ss_mem/ddr_aclk]
set design_clk [get_bd_pins $ss_mem/design_aclk]
connect_bd_net $pcie_aclk \
[get_bd_pins $ss_mem/pcie_aclk] \
[get_bd_pins $ss_reset/pcie_aclk] \
[get_bd_pins -of_objects $axi_ic_to_host -filter {TYPE == "clk" && DIR == "I"}] \
[get_bd_pins -of_objects $axi_ic_from_host -filter {TYPE == "clk" && DIR == "I" && NAME != "M00_ACLK"}] \
[get_bd_pins $ss_int/aclk] \
[get_bd_pins $tapasco_status/s00_axi_aclk]
set design_clk_receivers [list \
[get_bd_pins $ss_mem/design_clk] \
[get_bd_pins $ss_reset/design_aclk] \
[get_bd_pins uArch/*aclk] \
[get_bd_pins $axi_ic_from_host/M00_ACLK] \
]
if {[llength [arch::get_masters]] > 0} {
lappend design_clk_receivers [get_bd_pins -filter { TYPE == "clk" } -of_objects $axi_ic_to_mem]
}
connect_bd_net $design_clk $design_clk_receivers
connect_bd_net $ddr_clk [get_bd_pins $ss_reset/ddr_aclk]
# connect PCIe resets
connect_bd_net [get_bd_pins $ss_pcie/pcie_aresetn] \
[get_bd_pins $ss_reset/pcie_aresetn] \
[get_bd_pins $tapasco_status/s00_axi_aresetn]
connect_bd_net [get_bd_pins $ss_mem/ddr_aresetn] \
[get_bd_pins $ss_reset/ddr_clk_aresetn] \
[get_bd_pins $ss_reset/design_clk_aresetn]
set pcie_p_aresetn [get_bd_pins $ss_reset/pcie_peripheral_aresetn]
set pcie_ic_aresetn [get_bd_pins $ss_reset/pcie_interconnect_aresetn]
connect_bd_net $pcie_p_aresetn \
[get_bd_pins $ss_mem/mem64_aresetn] \
[get_bd_pins -of_objects $axi_ic_to_host -filter {TYPE == "rst" && DIR == "I" && NAME != "ARESETN"}] \
[get_bd_pins -of_objects $axi_ic_from_host -filter {TYPE == "rst" && DIR == "I" && NAME != "M00_ARESETN"}] \
[get_bd_pins $ss_int/peripheral_aresetn] \
[get_bd_pins $ss_mem/pcie_peripheral_aresetn]
connect_bd_net $pcie_ic_aresetn \
[get_bd_pins $axi_ic_to_host/ARESETN] \
[get_bd_pins $ss_int/interconnect_aresetn]
# connect ddr_clk resets
set ddr_clk_p_aresetn [get_bd_pins $ss_reset/ddr_clk_peripheral_aresetn]
set ddr_clk_ic_aresetn [get_bd_pins $ss_reset/ddr_clk_interconnect_aresetn]
connect_bd_net [get_bd_pins $ss_reset/ddr_clk_peripheral_aresetn] [get_bd_pins $ss_mem/ddr_peripheral_aresetn]
connect_bd_net [get_bd_pins $ss_reset/ddr_clk_interconnect_aresetn] [get_bd_pins $ss_mem/ddr_interconnect_aresetn]
set design_clk_p_aresetn [get_bd_pins $ss_reset/design_clk_peripheral_aresetn]
set design_clk_ic_aresetn [get_bd_pins $ss_reset/design_clk_interconnect_aresetn]
set design_rst_receivers [list \
[get_bd_pins $ss_mem/design_peripheral_aresetn] \
[get_bd_pins uArch/*peripheral_aresetn] \
[get_bd_pins $axi_ic_from_host/M00_ARESETN] \
]
if {[llength [arch::get_masters]] > 0} {
lappend design_rst_receivers [get_bd_pins -filter {TYPE == "rst" && NAME != "ARESETN"} -of_objects $axi_ic_to_mem]
}
connect_bd_net $design_clk_p_aresetn $design_rst_receivers
connect_bd_net $design_clk_ic_aresetn \
[get_bd_pins $ss_mem/interconnect_aresetn] \
[get_bd_pins uArch/*interconnect_aresetn] \
[get_bd_pins $axi_ic_to_mem/ARESETN]
# connect AXI from host to system
connect_bd_intf_net [get_bd_intf_pins $ss_pcie/m_axi] [get_bd_intf_pins $axi_ic_from_host/S00_AXI]
connect_bd_intf_net [get_bd_intf_pins $axi_ic_from_host/M00_AXI] [get_bd_intf_pins uArch/S_AXI]
connect_bd_intf_net [get_bd_intf_pins $axi_ic_from_host/M01_AXI] [get_bd_intf_pins $ss_int/S_AXI]
connect_bd_intf_net [get_bd_intf_pins $axi_ic_from_host/M02_AXI] [get_bd_intf_pins $ss_mem/s_axi_ddma]
# connect AXI from system to host
connect_bd_intf_net [get_bd_intf_pins $ss_mem/m_axi_mem64] [get_bd_intf_pins $axi_ic_to_host/S00_AXI]
connect_bd_intf_net [get_bd_intf_pins $ss_int/M_AXI] [get_bd_intf_pins $axi_ic_to_host/S01_AXI]
connect_bd_intf_net [get_bd_intf_pins $axi_ic_to_host/M00_AXI] [get_bd_intf_pins $ss_pcie/s_axi]
# call plugins
tapasco::call_plugins "post-platform"
# validate the design
platform_address_map
validate_bd_design
save_bd_design
}
##################################################################
# MIG PRJ FILE TCL PROCs
##################################################################
......
......@@ -19,18 +19,7 @@
source -notrace $::env(TAPASCO_HOME)/platform/zynq/zynq.tcl
namespace eval platform {
namespace export create
namespace export max_masters
foreach f [glob -nocomplain -directory "$::env(TAPASCO_HOME)/platform/zc706/plugins" "*.tcl"] {
source -notrace $f
}
proc max_masters {} {