Commit c7b36058 authored by Jens Korinth's avatar Jens Korinth
Browse files

AxiFifoAdapter: Improve switching speed

* condition for switching of FIFOs led to 1-cycle delay
* now switching when either other FIFO empty, or dequeing
  in progress and exactly one element
* conditions are the same in both states
parent 7ce43604
......@@ -67,8 +67,8 @@ class AxiFifoAdapter(
io.maxi.readData.ready := maxi_rready
// true, if buffers will be empty next cycle
val switch_a = fifo_a.io.deq.ready && fifo_a.io.count <= UInt(1)
val switch_b = fifo_b.io.deq.ready && fifo_b.io.count <= UInt(1)
val switch_a = fifo_a.io.deq.ready && fifo_a.io.count === UInt(1)
val switch_b = fifo_b.io.deq.ready && fifo_b.io.count === UInt(1)
// true, if buffer fill should start next cycle
val fill_a = fifo_a.io.count === UInt(0) || switch_a
val fill_b = fifo_b.io.count === UInt(0) || switch_b
......@@ -91,7 +91,7 @@ class AxiFifoAdapter(
maxi_raddr_hs := Bool(false) // re-enable address handshake
// check if we can stay in fetch mode and flip buffers
when (Mux(!fifo_sel, switch_a, switch_b)) {
when (Mux(!fifo_sel, fill_a, fill_b)) {
// just flip buffers
fifo_sel := !fifo_sel
}
......@@ -103,7 +103,7 @@ class AxiFifoAdapter(
}
.otherwise { // wait-for-consumption state
// check fill state of deq FIFO: if empty, flip FIFOs
when (Mux(!fifo_sel, switch_a, switch_b)) {
when (Mux(!fifo_sel, fill_a, fill_b)) {
fifo_sel := !fifo_sel
}
// check fill state of other FIFO
......
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