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tapasco
tapasco
Commits
c8eea4e8
Commit
c8eea4e8
authored
Dec 20, 2017
by
Jens Korinth
Browse files
Implement short-hand for named bits
parent
4a038ecf
Changes
3
Hide whitespace changes
Inline
Side-by-side
src/main/scala/axi4lite/.RegisterFile.scala.swp
0 → 100644
View file @
c8eea4e8
File added
src/main/scala/axi4lite/Registers.scala
View file @
c8eea4e8
...
...
@@ -11,7 +11,11 @@ import Chisel.{Reg, UInt}
sealed
abstract
class
ControlRegister
(
_name
:
Option
[
String
],
bitfield
:
BitfieldMap
=
Map
())
{
/** Format description string for bitfield (if any). */
private
def
bf
:
String
=
bitfield
.
toList
.
sortWith
((
a
,
b
)
=>
a
.
_2
.
to
>
b
.
_2
.
to
)
map
(
e
=>
"_%d-%d:_ %s"
.
format
(
e
.
_2
.
to
,
e
.
_2
.
from
,
e
.
_1
)
if
(
e
.
_2
.
to
==
e
.
_2
.
from
)
{
"_%d:_ %s"
.
format
(
e
.
_2
.
to
,
e
.
_1
)
}
else
{
"_%d-%d:_ %s"
.
format
(
e
.
_2
.
to
,
e
.
_2
.
from
,
e
.
_1
)
}
)
mkString
(
" "
)
/** Name of the register. */
...
...
src/main/scala/axi4lite/package.scala
View file @
c8eea4e8
...
...
@@ -6,6 +6,15 @@ package object axi4lite {
require
(
to
>=
from
&&
from
>=
0
,
"BitRange: invalid range (%d, %d)"
.
format
(
to
,
from
))
def
overlapsWith
(
other
:
BitRange
)
:
Boolean
=
!(
to
<
other
.
from
||
from
>
other
.
to
)
}
/** Short-hand for single bit BitRanges. */
object
Bit
{
def
apply
(
bit
:
Int
)
:
BitRange
=
{
require
(
bit
>=
0
,
s
"BitRange: invalid bit ($bit)"
)
BitRange
(
bit
,
bit
)
}
}
/** Names for bit ranges. **/
type
BitfieldMap
=
Map
[
String
,
BitRange
]
}
Jens Korinth
@jk
mentioned in commit
17f0d672
·
Mar 05, 2018
mentioned in commit
17f0d672
mentioned in commit 17f0d67240ebf5d7e1d0be9162d272b04256c47d
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