Commit c8eea4e8 authored by Jens Korinth's avatar Jens Korinth
Browse files

Implement short-hand for named bits

parent 4a038ecf
......@@ -11,7 +11,11 @@ import Chisel.{Reg, UInt}
sealed abstract class ControlRegister(_name: Option[String], bitfield: BitfieldMap = Map()) {
/** Format description string for bitfield (if any). */
private def bf: String = bitfield.toList.sortWith((a, b) => a._2.to > b._2.to) map (e =>
"_%d-%d:_ %s".format(e._2.to, e._2.from, e._1)
if (e._2.to == e._2.from) {
"_%d:_ %s".format(e._2.to, e._1)
} else {
"_%d-%d:_ %s".format(e._2.to, e._2.from, e._1)
}
) mkString (" ")
/** Name of the register. */
......
......@@ -6,6 +6,15 @@ package object axi4lite {
require (to >= from && from >= 0, "BitRange: invalid range (%d, %d)".format(to, from))
def overlapsWith(other: BitRange): Boolean = !(to < other.from || from > other.to)
}
/** Short-hand for single bit BitRanges. */
object Bit {
def apply(bit: Int): BitRange = {
require (bit >= 0, s"BitRange: invalid bit ($bit)")
BitRange(bit, bit)
}
}
/** Names for bit ranges. **/
type BitfieldMap = Map[String, BitRange]
}
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment