Commit c93205fa authored by Torben Kalkhof's avatar Torben Kalkhof Committed by Carsten Heinz
Browse files

Move QDMA soft reset

parent a1aac2d2
...@@ -5,6 +5,28 @@ ...@@ -5,6 +5,28 @@
<spirit:name>QDMAConfigurator</spirit:name> <spirit:name>QDMAConfigurator</spirit:name>
<spirit:version>1.0</spirit:version> <spirit:version>1.0</spirit:version>
<spirit:busInterfaces> <spirit:busInterfaces>
<spirit:busInterface>
<spirit:name>dma_resetn</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
<spirit:master/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>dma_resetn</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>POLARITY</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.DMA_RESETN.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
<spirit:busInterface> <spirit:busInterface>
<spirit:name>resetn</spirit:name> <spirit:name>resetn</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/> <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
...@@ -27,6 +49,22 @@ ...@@ -27,6 +49,22 @@
</spirit:parameter> </spirit:parameter>
</spirit:parameters> </spirit:parameters>
</spirit:busInterface> </spirit:busInterface>
<spirit:busInterface>
<spirit:name>start_reset</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>start_reset</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
</spirit:busInterface>
<spirit:busInterface> <spirit:busInterface>
<spirit:name>clk</spirit:name> <spirit:name>clk</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/> <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
...@@ -208,7 +246,7 @@ ...@@ -208,7 +246,7 @@
<spirit:parameters> <spirit:parameters>
<spirit:parameter> <spirit:parameter>
<spirit:name>viewChecksum</spirit:name> <spirit:name>viewChecksum</spirit:name>
<spirit:value>13d7c716</spirit:value> <spirit:value>64e1c25e</spirit:value>
</spirit:parameter> </spirit:parameter>
</spirit:parameters> </spirit:parameters>
</spirit:view> </spirit:view>
...@@ -224,7 +262,7 @@ ...@@ -224,7 +262,7 @@
<spirit:parameters> <spirit:parameters>
<spirit:parameter> <spirit:parameter>
<spirit:name>viewChecksum</spirit:name> <spirit:name>viewChecksum</spirit:name>
<spirit:value>13d7c716</spirit:value> <spirit:value>64e1c25e</spirit:value>
</spirit:parameter> </spirit:parameter>
</spirit:parameters> </spirit:parameters>
</spirit:view> </spirit:view>
...@@ -522,6 +560,32 @@ ...@@ -522,6 +560,32 @@
</spirit:wireTypeDefs> </spirit:wireTypeDefs>
</spirit:wire> </spirit:wire>
</spirit:port> </spirit:port>
<spirit:port>
<spirit:name>start_reset</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>dma_resetn</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
</spirit:ports> </spirit:ports>
</spirit:model> </spirit:model>
<spirit:choices> <spirit:choices>
...@@ -537,7 +601,7 @@ ...@@ -537,7 +601,7 @@
<spirit:file> <spirit:file>
<spirit:name>src/mkQDMAConfigurator.v</spirit:name> <spirit:name>src/mkQDMAConfigurator.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType> <spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>CHECKSUM_13d7c716</spirit:userFileType> <spirit:userFileType>CHECKSUM_64e1c25e</spirit:userFileType>
</spirit:file> </spirit:file>
</spirit:fileSet> </spirit:fileSet>
<spirit:fileSet> <spirit:fileSet>
...@@ -595,16 +659,16 @@ ...@@ -595,16 +659,16 @@
<xilinx:displayName>QDMAConfigurator</xilinx:displayName> <xilinx:displayName>QDMAConfigurator</xilinx:displayName>
<xilinx:definitionSource>package_project</xilinx:definitionSource> <xilinx:definitionSource>package_project</xilinx:definitionSource>
<xilinx:coreRevision>1</xilinx:coreRevision> <xilinx:coreRevision>1</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2022-04-09T17:39:03Z</xilinx:coreCreationDateTime> <xilinx:coreCreationDateTime>2022-04-27T11:33:01Z</xilinx:coreCreationDateTime>
<xilinx:tags> <xilinx:tags>
<xilinx:tag xilinx:name="nopcore"/> <xilinx:tag xilinx:name="nopcore"/>
</xilinx:tags> </xilinx:tags>
</xilinx:coreExtensions> </xilinx:coreExtensions>
<xilinx:packagingInfo> <xilinx:packagingInfo>
<xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion> <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="47dac921"/> <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="b7768877"/>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="9541f876"/> <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="b4b0e274"/>
<xilinx:checksum xilinx:scope="ports" xilinx:value="aff99cf8"/> <xilinx:checksum xilinx:scope="ports" xilinx:value="ed896dca"/>
<xilinx:checksum xilinx:scope="parameters" xilinx:value="6efacd4e"/> <xilinx:checksum xilinx:scope="parameters" xilinx:value="6efacd4e"/>
</xilinx:packagingInfo> </xilinx:packagingInfo>
</spirit:vendorExtensions> </spirit:vendorExtensions>
......
// //
// Generated by Bluespec Compiler, version 2022.01 (build 066c7a8) // Generated by Bluespec Compiler, version 2022.01 (build 066c7a8)
// //
// On Sat Apr 9 17:38:37 UTC 2022 // On Wed Apr 27 11:32:37 UTC 2022
// //
// //
// Ports: // Ports:
...@@ -19,11 +19,13 @@ ...@@ -19,11 +19,13 @@
// msix_vectors_per_vfg2 O 32 const // msix_vectors_per_vfg2 O 32 const
// msix_vectors_per_vfg3 O 32 const // msix_vectors_per_vfg3 O 32 const
// numvec_valid O 1 reg // numvec_valid O 1 reg
// dma_resetn O 1 reg
// clk I 1 clock // clk I 1 clock
// resetn I 1 reset // resetn I 1 reset
// drp_rdy I 1 reg // drp_rdy I 1 reg
// drp_di I 16 unused // drp_di I 16 unused
// numvec_done I 1 reg // numvec_done I 1 reg
// start_reset I 1 reg
// //
// No combinational paths from inputs to outputs // No combinational paths from inputs to outputs
// //
...@@ -75,7 +77,11 @@ module mkQDMAConfigurator(clk, ...@@ -75,7 +77,11 @@ module mkQDMAConfigurator(clk,
numvec_valid, numvec_valid,
numvec_done); numvec_done,
start_reset,
dma_resetn);
input clk; input clk;
input resetn; input resetn;
...@@ -127,6 +133,12 @@ module mkQDMAConfigurator(clk, ...@@ -127,6 +133,12 @@ module mkQDMAConfigurator(clk,
// action method msix_vec_ctrl_acceptDone // action method msix_vec_ctrl_acceptDone
input numvec_done; input numvec_done;
// action method trigger
input start_reset;
// value method dma_resetn
output dma_resetn;
// signals for module outputs // signals for module outputs
wire [31 : 0] msix_vectors_per_pf0, wire [31 : 0] msix_vectors_per_pf0,
msix_vectors_per_pf1, msix_vectors_per_pf1,
...@@ -138,7 +150,16 @@ module mkQDMAConfigurator(clk, ...@@ -138,7 +150,16 @@ module mkQDMAConfigurator(clk,
msix_vectors_per_vfg3; msix_vectors_per_vfg3;
wire [15 : 0] drp_do; wire [15 : 0] drp_do;
wire [10 : 0] drp_addr; wire [10 : 0] drp_addr;
wire drp_en, drp_we, numvec_valid; wire dma_resetn, drp_en, drp_we, numvec_valid;
// register count
reg [7 : 0] count;
reg [7 : 0] count$D_IN;
wire count$EN;
// register dmaResetN
reg dmaResetN;
wire dmaResetN$D_IN, dmaResetN$EN;
// register drpEn // register drpEn
reg drpEn; reg drpEn;
...@@ -148,6 +169,11 @@ module mkQDMAConfigurator(clk, ...@@ -148,6 +169,11 @@ module mkQDMAConfigurator(clk,
reg drpRdy; reg drpRdy;
wire drpRdy$D_IN, drpRdy$EN; wire drpRdy$D_IN, drpRdy$EN;
// register drpState
reg [1 : 0] drpState;
reg [1 : 0] drpState$D_IN;
wire drpState$EN;
// register drpWE // register drpWE
reg drpWE; reg drpWE;
wire drpWE$D_IN, drpWE$EN; wire drpWE$D_IN, drpWE$EN;
...@@ -160,13 +186,28 @@ module mkQDMAConfigurator(clk, ...@@ -160,13 +186,28 @@ module mkQDMAConfigurator(clk,
reg numvecValid; reg numvecValid;
wire numvecValid$D_IN, numvecValid$EN; wire numvecValid$D_IN, numvecValid$EN;
// register state // register startReset
reg [2 : 0] state; reg startReset;
reg [2 : 0] state$D_IN; wire startReset$D_IN, startReset$EN;
wire state$EN;
// register vecState
reg [1 : 0] vecState;
reg [1 : 0] vecState$D_IN;
wire vecState$EN;
// rule scheduling signals // rule scheduling signals
wire WILL_FIRE_RL_finishDrpWrite, WILL_FIRE_RL_startDrp; wire WILL_FIRE_RL_finishDrpWrite,
WILL_FIRE_RL_finishResetCycle,
WILL_FIRE_RL_startResetCycle;
// inputs to muxes for submodule ports
wire [7 : 0] MUX_count$write_1__VAL_1, MUX_count$write_1__VAL_2;
wire MUX_count$write_1__SEL_1,
MUX_dmaResetN$write_1__SEL_1,
MUX_numvecValid$write_1__SEL_1;
// remaining internal signals
wire count_2_ULT_128___d13, count_2_ULT_16___d18;
// value method drp_drp_addr // value method drp_drp_addr
assign drp_addr = 11'd213 ; assign drp_addr = 11'd213 ;
...@@ -207,46 +248,113 @@ module mkQDMAConfigurator(clk, ...@@ -207,46 +248,113 @@ module mkQDMAConfigurator(clk,
// value method msix_vec_ctrl_numvec_valid // value method msix_vec_ctrl_numvec_valid
assign numvec_valid = numvecValid ; assign numvec_valid = numvecValid ;
// rule RL_startDrp // value method dma_resetn
assign WILL_FIRE_RL_startDrp = state == 3'd3 && numvecDone ; assign dma_resetn = dmaResetN ;
// rule RL_finishDrpWrite // rule RL_finishDrpWrite
assign WILL_FIRE_RL_finishDrpWrite = state == 3'd2 && drpRdy ; assign WILL_FIRE_RL_finishDrpWrite = drpState == 2'd2 && drpRdy ;
// rule RL_startResetCycle
assign WILL_FIRE_RL_startResetCycle = vecState == 2'd0 && startReset ;
// rule RL_finishResetCycle
assign WILL_FIRE_RL_finishResetCycle = vecState == 2'd3 && numvecDone ;
// inputs to muxes for submodule ports
assign MUX_count$write_1__SEL_1 = vecState == 2'd2 && count_2_ULT_16___d18 ;
assign MUX_dmaResetN$write_1__SEL_1 =
vecState == 2'd1 && !count_2_ULT_128___d13 ;
assign MUX_numvecValid$write_1__SEL_1 =
vecState == 2'd2 && !count_2_ULT_16___d18 ;
assign MUX_count$write_1__VAL_1 = count + 8'd1 ;
assign MUX_count$write_1__VAL_2 =
count_2_ULT_128___d13 ? count + 8'd1 : 8'd0 ;
// register count
always@(MUX_count$write_1__SEL_1 or
MUX_count$write_1__VAL_1 or
vecState or
MUX_count$write_1__VAL_2 or WILL_FIRE_RL_startResetCycle)
begin
case (1'b1) // synopsys parallel_case
MUX_count$write_1__SEL_1: count$D_IN = MUX_count$write_1__VAL_1;
vecState == 2'd1: count$D_IN = MUX_count$write_1__VAL_2;
WILL_FIRE_RL_startResetCycle: count$D_IN = 8'd0;
default: count$D_IN = 8'b10101010 /* unspecified value */ ;
endcase
end
assign count$EN =
vecState == 2'd2 && count_2_ULT_16___d18 || vecState == 2'd1 ||
WILL_FIRE_RL_startResetCycle ;
// register dmaResetN
assign dmaResetN$D_IN = MUX_dmaResetN$write_1__SEL_1 ;
assign dmaResetN$EN =
vecState == 2'd1 && !count_2_ULT_128___d13 ||
WILL_FIRE_RL_startResetCycle ;
// register drpEn // register drpEn
assign drpEn$D_IN = state != 3'd1 ; assign drpEn$D_IN = drpState != 2'd1 ;
assign drpEn$EN = state == 3'd1 || WILL_FIRE_RL_startDrp ; assign drpEn$EN = drpState == 2'd1 || drpState == 2'd0 ;
// register drpRdy // register drpRdy
assign drpRdy$D_IN = drp_rdy ; assign drpRdy$D_IN = drp_rdy ;
assign drpRdy$EN = 1'd1 ; assign drpRdy$EN = 1'd1 ;
// register drpState
always@(drpState or WILL_FIRE_RL_finishDrpWrite)
begin
case (1'b1) // synopsys parallel_case
drpState == 2'd0: drpState$D_IN = 2'd1;
drpState == 2'd1: drpState$D_IN = 2'd2;
WILL_FIRE_RL_finishDrpWrite: drpState$D_IN = 2'd3;
default: drpState$D_IN = 2'b10 /* unspecified value */ ;
endcase
end
assign drpState$EN =
drpState == 2'd0 || drpState == 2'd1 ||
WILL_FIRE_RL_finishDrpWrite ;
// register drpWE // register drpWE
assign drpWE$D_IN = state != 3'd1 ; assign drpWE$D_IN = drpState != 2'd1 ;
assign drpWE$EN = state == 3'd1 || WILL_FIRE_RL_startDrp ; assign drpWE$EN = drpState == 2'd1 || drpState == 2'd0 ;
// register numvecDone // register numvecDone
assign numvecDone$D_IN = numvec_done ; assign numvecDone$D_IN = numvec_done ;
assign numvecDone$EN = 1'd1 ; assign numvecDone$EN = 1'd1 ;
// register numvecValid // register numvecValid
assign numvecValid$D_IN = !WILL_FIRE_RL_startDrp ; assign numvecValid$D_IN = MUX_numvecValid$write_1__SEL_1 ;
assign numvecValid$EN = WILL_FIRE_RL_startDrp || state == 3'd0 ; assign numvecValid$EN =
vecState == 2'd2 && !count_2_ULT_16___d18 ||
// register state WILL_FIRE_RL_finishResetCycle ;
always@(WILL_FIRE_RL_startDrp or state or WILL_FIRE_RL_finishDrpWrite)
// register startReset
assign startReset$D_IN = start_reset ;
assign startReset$EN = 1'd1 ;
// register vecState
always@(MUX_dmaResetN$write_1__SEL_1 or
MUX_numvecValid$write_1__SEL_1 or
WILL_FIRE_RL_finishResetCycle or WILL_FIRE_RL_startResetCycle)
begin begin
case (1'b1) // synopsys parallel_case case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_startDrp: state$D_IN = 3'd1; MUX_dmaResetN$write_1__SEL_1: vecState$D_IN = 2'd2;
state == 3'd1: state$D_IN = 3'd2; MUX_numvecValid$write_1__SEL_1: vecState$D_IN = 2'd3;
state == 3'd0: state$D_IN = 3'd3; WILL_FIRE_RL_finishResetCycle: vecState$D_IN = 2'd0;
WILL_FIRE_RL_finishDrpWrite: state$D_IN = 3'd4; WILL_FIRE_RL_startResetCycle: vecState$D_IN = 2'd1;
default: state$D_IN = 3'b010 /* unspecified value */ ; default: vecState$D_IN = 2'b10 /* unspecified value */ ;
endcase endcase
end end
assign state$EN = assign vecState$EN =
WILL_FIRE_RL_startDrp || state == 3'd1 || state == 3'd0 || vecState == 2'd1 && !count_2_ULT_128___d13 ||
WILL_FIRE_RL_finishDrpWrite ; vecState == 2'd2 && !count_2_ULT_16___d18 ||
WILL_FIRE_RL_finishResetCycle ||
WILL_FIRE_RL_startResetCycle ;
// remaining internal signals
assign count_2_ULT_128___d13 = count < 8'd128 ;
assign count_2_ULT_16___d18 = count < 8'd16 ;
// handling of inlined registers // handling of inlined registers
...@@ -254,23 +362,32 @@ module mkQDMAConfigurator(clk, ...@@ -254,23 +362,32 @@ module mkQDMAConfigurator(clk,
begin begin
if (resetn == `BSV_RESET_VALUE) if (resetn == `BSV_RESET_VALUE)
begin begin
drpEn <= `BSV_ASSIGNMENT_DELAY 1'd0; count <= `BSV_ASSIGNMENT_DELAY 8'd0;
dmaResetN <= `BSV_ASSIGNMENT_DELAY 1'd1;
drpEn <= `BSV_ASSIGNMENT_DELAY 1'd0;
drpRdy <= `BSV_ASSIGNMENT_DELAY 1'd0; drpRdy <= `BSV_ASSIGNMENT_DELAY 1'd0;
drpState <= `BSV_ASSIGNMENT_DELAY 2'd0;
drpWE <= `BSV_ASSIGNMENT_DELAY 1'd0; drpWE <= `BSV_ASSIGNMENT_DELAY 1'd0;
numvecDone <= `BSV_ASSIGNMENT_DELAY 1'd0; numvecDone <= `BSV_ASSIGNMENT_DELAY 1'd0;
numvecValid <= `BSV_ASSIGNMENT_DELAY 1'd0; numvecValid <= `BSV_ASSIGNMENT_DELAY 1'd0;
state <= `BSV_ASSIGNMENT_DELAY 3'd0; startReset <= `BSV_ASSIGNMENT_DELAY 1'd0;
vecState <= `BSV_ASSIGNMENT_DELAY 2'd0;
end end
else else
begin begin
if (drpEn$EN) drpEn <= `BSV_ASSIGNMENT_DELAY drpEn$D_IN; if (count$EN) count <= `BSV_ASSIGNMENT_DELAY count$D_IN;
if (dmaResetN$EN) dmaResetN <= `BSV_ASSIGNMENT_DELAY dmaResetN$D_IN;
if (drpEn$EN) drpEn <= `BSV_ASSIGNMENT_DELAY drpEn$D_IN;
if (drpRdy$EN) drpRdy <= `BSV_ASSIGNMENT_DELAY drpRdy$D_IN; if (drpRdy$EN) drpRdy <= `BSV_ASSIGNMENT_DELAY drpRdy$D_IN;
if (drpState$EN) drpState <= `BSV_ASSIGNMENT_DELAY drpState$D_IN;
if (drpWE$EN) drpWE <= `BSV_ASSIGNMENT_DELAY drpWE$D_IN; if (drpWE$EN) drpWE <= `BSV_ASSIGNMENT_DELAY drpWE$D_IN;
if (numvecDone$EN) if (numvecDone$EN)
numvecDone <= `BSV_ASSIGNMENT_DELAY numvecDone$D_IN; numvecDone <= `BSV_ASSIGNMENT_DELAY numvecDone$D_IN;
if (numvecValid$EN) if (numvecValid$EN)
numvecValid <= `BSV_ASSIGNMENT_DELAY numvecValid$D_IN; numvecValid <= `BSV_ASSIGNMENT_DELAY numvecValid$D_IN;
if (state$EN) state <= `BSV_ASSIGNMENT_DELAY state$D_IN; if (startReset$EN)
startReset <= `BSV_ASSIGNMENT_DELAY startReset$D_IN;
if (vecState$EN) vecState <= `BSV_ASSIGNMENT_DELAY vecState$D_IN;
end end
end end
...@@ -279,12 +396,16 @@ module mkQDMAConfigurator(clk, ...@@ -279,12 +396,16 @@ module mkQDMAConfigurator(clk,
`else // not BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS
initial initial
begin begin
count = 8'hAA;
dmaResetN = 1'h0;
drpEn = 1'h0; drpEn = 1'h0;
drpRdy = 1'h0; drpRdy = 1'h0;
drpState = 2'h2;
drpWE = 1'h0; drpWE = 1'h0;
numvecDone = 1'h0; numvecDone = 1'h0;
numvecValid = 1'h0; numvecValid = 1'h0;
state = 3'h2; startReset = 1'h0;
vecState = 2'h2;
end end
`endif // BSV_NO_INITIAL_BLOCKS `endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on // synopsys translate_on
......
...@@ -167,28 +167,6 @@ ...@@ -167,28 +167,6 @@
</spirit:portMap> </spirit:portMap>
</spirit:portMaps> </spirit:portMaps>
</spirit:busInterface> </spirit:busInterface>
<spirit:busInterface>
<spirit:name>dma_resetn</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
<spirit:master/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>dma_resetn</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>POLARITY</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.DMA_RESETN.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
<spirit:busInterface> <spirit:busInterface>
<spirit:name>resetn</spirit:name> <spirit:name>resetn</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/> <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
...@@ -860,7 +838,7 @@ ...@@ -860,7 +838,7 @@
<spirit:parameters> <spirit:parameters>
<spirit:parameter> <spirit:parameter>
<spirit:name>viewChecksum</spirit:name> <spirit:name>viewChecksum</spirit:name>
<spirit:value>424bb295</spirit:value> <spirit:value>d7a4257f</spirit:value>
</spirit:parameter> </spirit:parameter>
</spirit:parameters> </spirit:parameters>
</spirit:view> </spirit:view>
...@@ -876,7 +854,7 @@ ...@@ -876,7 +854,7 @@
<spirit:parameters> <spirit:parameters>
<spirit:parameter>