Commit cdb31373 authored by Jaco Hofmann's avatar Jaco Hofmann
Browse files

Merges changes from branch 2017.2 into MPSoC

parents c05d1317 d2d5bf12
......@@ -39,3 +39,7 @@ boot/zedboard
boot/rootfs.img
boot/uenv/uEnv-pynq.txt
project/build.properties
bin/itapasco
bin/tapasco
bin/tapasco-logviewer
bin/tapasco-reportviewer
# This file is a template, and might need editing before it works on your project.
# Official Java image. Look for the different tagged releases at
# https://hub.docker.com/r/library/java/tags/ . A Java image is not required
# but an image with a JVM speeds up the build a bit.
image: java:8
before_script:
# Enable the usage of sources over https
- apt-get update -yqq
- apt-get install apt-transport-https zip -yqq
# Add keyserver for SBT
- echo "deb http://dl.bintray.com/sbt/debian /" | tee -a /etc/apt/sources.list.d/sbt.list
- apt-key adv --keyserver hkp://keyserver.ubuntu.com:80 --recv 2EE0EA64E40A89B84B2DF73499E82A75642AC823
# Install SBT
- curl -s "https://get.sdkman.io" | bash
- source "/root/.sdkman/bin/sdkman-init.sh"
- sdk install sbt
# Log the sbt version
- sbt version
test:
script:
# Execute your project's tests
- source setup.sh
- sbt clean test
......@@ -117,6 +117,13 @@ namespace eval arch {
return $insts
}
# Retrieve AXI-MM interfaces of given instance of kernel kind and mode.
proc get_aximm_interfaces {kind inst {mode "Master"}} {
set name [format "target_ip_%02d_%03d" $kind $inst]
puts "Retrieving list of slave interfaces for $name ..."
return [tapasco::get_aximm_interfaces [get_bd_cell -hier -filter "NAME == $name"] $mode]
}
# Instantiates the memory interconnect hierarchy.
proc arch_create_mem_interconnects {composition outs} {
variable arch_mem_ports
......@@ -132,8 +139,22 @@ namespace eval arch {
set masters [tapasco::get_aximm_interfaces $example]
set ic_m [expr "$ic_m + [llength $masters] * $no_inst"]
set masters_32b [get_bd_intf_pins -of_objects $example -filter { MODE == "Master" && VLNV == "xilinx.com:interface:aximm_rtl:1.0" && CONFIG.DATA_WIDTH == 32 }]
set masters_64b [get_bd_intf_pins -of_objects $example -filter { MODE == "Master" && VLNV == "xilinx.com:interface:aximm_rtl:1.0" && CONFIG.DATA_WIDTH == 64 }]
set masters_32b {}
set masters_64b {}
set masters_oth {}
foreach m $masters {
set dw [tapasco::get_aximm_property CONFIG.DATA_WIDTH $m]
if {$dw == 64} {
lappend masters_64b $m
} else {
if {$dw == 32} {
lappend masters_32b $m
} else {
lappend masters_oth $m
}
}
}
set m32 [expr "$m32 + [llength $masters_32b] * $no_inst"]
set m64 [expr "$m64 + [llength $masters_64b] * $no_inst"]
}
......
#
# Copyright (C) 2017 Jens Korinth, TU Darmstadt
#
# This file is part of Tapasco (TPC).
#
# Tapasco is free software: you can redistribute it and/or modify
# it under the terms of the GNU Lesser General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# Tapasco is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU Lesser General Public License for more details.
#
# You should have received a copy of the GNU Lesser General Public License
# along with Tapasco. If not, see <http://www.gnu.org/licenses/>.
#
# @file mb_shifter.tcl
# @brief Plugin to insert the MicroBlaze Debug Module (MDM) for all DEBUG ports
# found in the Architecture.
# @author J. Korinth, TU Darmstadt (jk@esa.cs.tu-darmstadt.de)
#
namespace eval debug {
proc debug_feature {args} {
if {[tapasco::is_feature_enabled "Debug"]} {
# set defaults
set depth 1024
set stages 0
set interfaces {}
set debug [tapasco::get_feature "Debug"]
dict with debug {
set num_ifs [llength $interfaces]
if {$num_ifs > 0} {
set i 0
foreach ifs $interfaces {
if {[llength $ifs] == 3} {
set s_ila [tapasco::createSystemILA "SILA_$i" $num_ifs $depth $stages]
puts " ifs = $ifs"
set intf [get_bd_intf_pins [lindex $ifs 0]]
set clk [get_bd_pins [lindex $ifs 1]]
set rst [get_bd_pins [lindex $ifs 2]]
puts " connecting $intf to port #$i, clock to $clk, reset to $rst ..."
connect_bd_intf_net $intf [get_bd_intf_pins "$s_ila/SLOT_${i}_AXI"]
connect_bd_net $clk [get_bd_pins -of_objects $s_ila -filter {TYPE == clk && DIR == I}]
connect_bd_net $rst [get_bd_pins -of_objects $s_ila -filter {TYPE == rst && DIR == I}]
incr i
} else {
error "expected three elements for debugging interface: interface, clock and reset; found: $ifs"
}
}
}
}
}
}
}
tapasco::register_plugin "arch::debug::debug_feature" "post-bd"
......@@ -26,7 +26,7 @@ namespace eval full_axi_wrapper {
# check interfaces: AXI3/AXI4 slaves will be wrappped
set inst [get_bd_cells $inst]
set full_slave_ifs [get_bd_intf_pins -of_objects $inst -filter {MODE == Slave && (CONFIG.PROTOCOL == AXI3 || CONFIG.PROTOCOL == AXI4)}]
if {[llength $full_slave_ifs] > 1} { error "full_axi_wrapper plugin: Found [llength $full_slave_ifs] full slave interfaces, this is not supported at the moment" }
# if {[llength $full_slave_ifs] > 1} { error "full_axi_wrapper plugin: Found [llength $full_slave_ifs] full slave interfaces, this is not supported at the moment" }
if {[llength $full_slave_ifs] > 0} {
puts " IP has full slaves, will add protocol converter"
puts " found full slave interfaces: $full_slave_ifs"
......@@ -39,12 +39,27 @@ namespace eval full_axi_wrapper {
move_bd_cells $group $inst
set ninst [get_bd_cells $group/internal_$name]
current_bd_instance $group
# create slave ports
set saxi_port [create_bd_intf_pin -vlnv "xilinx.com:interface:aximm_rtl:1.0" -mode Slave "S_AXI_LITE"]
set conv [tapasco::createProtocolConverter "conv" "AXI4LITE" [get_property CONFIG.PROTOCOL $full_slave_ifs]]
connect_bd_intf_net $saxi_port [get_bd_intf_pins -of_objects $conv -filter {MODE == Slave}]
connect_bd_intf_net [get_bd_intf_pins -filter {MODE == Master} -of_objects $conv] $full_slave_ifs
# rewire full slaves
set si 0
foreach fs $full_slave_ifs {
# create slave port
set saxi_port [create_bd_intf_pin -vlnv "xilinx.com:interface:aximm_rtl:1.0" -mode Slave "S_AXI_LITE_$si"]
set conv [tapasco::createProtocolConverter "conv_$si" "AXI4LITE" [get_property CONFIG.PROTOCOL $fs]]
connect_bd_intf_net $saxi_port [get_bd_intf_pins -of_objects $conv -filter {MODE == Slave}]
connect_bd_intf_net [get_bd_intf_pins -filter {MODE == Master} -of_objects $conv] $fs
incr si
}
# bypass existing AXI4Lite slaves
set lite_ports [list]
set lites [get_bd_intf_pins -of_objects $inst -filter {MODE == Slave && CONFIG.PROTOCOL == AXI4LITE}]
foreach ls $lites {
set op [create_bd_intf_pin -vlnv "xilinx.com:interface:aximm_rtl:1.0" -mode Slave [get_property NAME $ls]]
connect_bd_intf_net $op $ls
lappend lite_ports $ls
}
puts "lite_ports = $lite_ports"
# create master ports
set maxi_ports [list]
......@@ -57,7 +72,7 @@ namespace eval full_axi_wrapper {
# create clock and reset ports
set clks [get_bd_pins -filter {DIR == I && TYPE == clk} -of_objects [get_bd_cells $group/*]]
set rsts [get_bd_pins -filter {DIR == I && TYPE == rst} -of_objects [get_bd_cells $group/*]]
set rsts [get_bd_pins -filter {DIR == I && TYPE == rst && CONFIG.POLARITY == ACTIVE_LOW} -of_objects [get_bd_cells $group/*]]
set clk [create_bd_pin -type clk -dir I "aclk"]
set rst [create_bd_pin -type rst -dir I "aresetn"]
......@@ -72,6 +87,11 @@ namespace eval full_axi_wrapper {
}
return [list $inst $args]
}
proc fix_address_map {} {
assign_bd_address
}
}
tapasco::register_plugin "arch::full_axi_wrapper::wrap_full_axi_interfaces" "post-pe-create"
tapasco::register_plugin "arch::full_axi_wrapper::fix_address_map" "pre-platform"
......@@ -12,7 +12,7 @@ parser.add_argument('--verbose', help='verbose output (default: %(default)s)', a
args = parser.parse_args()
if not os.path.exists(args.bitstream):
sys.exit('ERROR: {0} does could not be opened'.format(args.bitstream))
sys.exit('ERROR: {0} could not be opened'.format(args.bitstream))
if not 'TAPASCO_PLATFORM' in os.environ:
print('Environment variable TAPASCO_PLATFORM is not set, guessing Platform ...')
......
#!/bin/bash
#!/bin/bash -x
BOARD=${1:-zedboard}
VERSION=${2:-2016.4}
IMGSIZE=${3:-8192}
......@@ -389,9 +389,11 @@ EOF
fi
echo "Unmounting image in $LOOPDEV ..."
dusudo losetup -d $LOOPDEV
dusudo sync
echo "Mounting partitions in $OUTPUT_IMAGE ..."
dusudo kpartx -a $OUTPUT_IMAGE ||
dusudo kpartx -av $OUTPUT_IMAGE ||
return $(error_ret "$LINENO: could not kpartx -a $OUTPUT_IMAGE")
sleep 3
LD=`basename $LOOPDEV`
LD1=${LD}p1
LD2=${LD}p2
......@@ -470,7 +472,7 @@ copy_files_to_root () {
dusudo sh -c "echo $BOARD > $TO/etc/hostname" ||
echo >&2 "$LINENO: WARNING: could not set hostname"
echo "Updating /etc/hosts ..."
dusudo sed -i "s/pynq/$BOARD/g" $TO/etc/hosts ||
dusudo sh -c "sed -i "s/pynq/$BOARD/g" $TO/etc/hosts" ||
echo >&2 "$LINENO: WARNING: could not update /etc/hosts"
echo "Setting env vars ... "
dusudo sh -c "echo export LINUX_HOME=/linux-xlnx >> $TO/home/xilinx/.bashrc" ||
......@@ -515,6 +517,7 @@ check_image_tools
check_sdcard
read -p "Enter sudo password: " -s SUDOPW
[[ -n $SUDOPW ]] || error_exit "dusudo password may not be empty"
dusudo true || error_exit "sudo password seems to be wrong?"
mkdir -p $LOGDIR 2> /dev/null
mkdir -p `dirname $PYNQ_IMAGE` 2> /dev/null
echo "And so it begins ..."
......@@ -589,7 +592,7 @@ extract_pynq_rootfs &> $EXTRACT_RFS_LOG
echo "Building image in $OUTPUT_IMAGE (output in $BUILD_OUTPUT_IMAGE_LOG) ..."
build_output_image $IMGSIZE &> $BUILD_OUTPUT_IMAGE_LOG
if [[ $? -ne 0 ]]; then
# rm -f $OUTPUT_IMAGE &> /dev/null
rm -f $OUTPUT_IMAGE &> /dev/null
error_exit "Building output image failed, check log: $BUILD_OUTPUT_IMAGE_LOG"
fi
echo "SD card image ready: $OUTPUT_IMAGE"
......
......@@ -6,25 +6,24 @@ version := tapascoVersion
name := "Tapasco"
scalaVersion := "2.12.3"
scalaVersion := "2.12.4"
libraryDependencies ++= Seq(
"org.scala-lang" % "scala-compiler" % scalaVersion.value,
"org.scala-lang" % "scala-reflect" % scalaVersion.value,
"org.scala-lang.modules" % "scala-swing_2.12" % "2.0.0",
"org.scala-lang.modules" %% "scala-parser-combinators" % "1.0.4",
"com.typesafe.play" %% "play-json" % "2.6.0-M3" exclude ("ch.qos.logback", "logback-classic"),
"org.scala-lang.modules" % "scala-swing_2.12" % "2.0.1",
"com.typesafe.play" %% "play-json" % "2.6.7" exclude ("ch.qos.logback", "logback-classic"),
"org.jfree" % "jfreechart" % "1.0.19",
"org.slf4j" % "slf4j-api" % "1.7.22",
"ch.qos.logback" % "logback-classic" % "1.2.1",
"org.slf4j" % "slf4j-api" % "1.7.25",
"ch.qos.logback" % "logback-classic" % "1.2.3",
"net.sf.jung" % "jung-api" % "2.1.1",
"net.sf.jung" % "jung-visualization" % "2.1.1",
"net.sf.jung" % "jung-graph-impl" % "2.1.1",
"com.google.guava" % "guava" % "19.0",
"com.google.code.findbugs" % "jsr305" % "3.0.1",
"org.scalatest" %% "scalatest" % "3.0.3" % "test",
"org.scalatest" %% "scalatest" % "3.0.4" % "test",
"org.scalacheck" %% "scalacheck" % "1.13.5" % "test",
"com.lihaoyi" %% "fastparse" % "0.4.3"
"com.lihaoyi" %% "fastparse" % "1.0.0"
)
scalacOptions ++= Seq(
......
......@@ -70,7 +70,7 @@ namespace eval tapasco {
# Returns the Tapasco version.
proc get_tapasco_version {} {
return "2017.1"
return "2017.2"
}
# Instantiates an AXI Interconnect IP.
......@@ -424,6 +424,16 @@ namespace eval tapasco {
}
}
# make map of IDs -> number of slave interfaces
set composition [tapasco::get_composition]
set no_kinds [llength [dict keys $composition]]
set no_slaves [list]
for {set i 0} {$i < $no_kinds} {incr i} {
lappend no_slaves [dict get $composition $i id]
lappend no_slaves [llength [arch::get_aximm_interfaces $i 0 "Slave"]]
}
puts " Slvs: $no_slaves"
# create the IP core
set inst [create_bd_cell -type ip -vlnv [dict get $stdcomps tapasco_status vlnv] $name]
# make properties list
......@@ -434,7 +444,7 @@ namespace eval tapasco {
if {$slot < 128} {
lappend props "[format CONFIG.C_SLOT_KERNEL_ID_%d [expr $slot + 1]]" "$i"
}
incr slot
incr slot [dict get $no_slaves $i]
}
# get version strings
set vversion [split [version -short] {.}]
......@@ -535,6 +545,26 @@ namespace eval tapasco {
return $inst
}
# Instantiates a System ILA core for AXI debugging.
# @param name Name of the instance
# @param ports Number of ports (optional, default: 1)
# @param depth Data depth (optional, default: 1024)
# @param stages Input pipeline stages (optional, default: 0)
# @return block design cell (or error)
proc createSystemILA {name {ports 1} {depth 1024} {stages 0}} {
variable stdcomps
puts "Creating System ILA $name ..."
set vlnv [dict get $stdcomps system_ila vlnv]
puts " VLNV: $vlnv"
set inst [create_bd_cell -type ip -vlnv $vlnv $name]
set_property -dict [list \
CONFIG.C_NUM_MONITOR_SLOTS $ports \
CONFIG.C_DATA_DEPTH $depth \
CONFIG.C_INPUT_PIPE_STAGES $stages \
] $inst
return $inst
}
# Returns the interface pin groups for all AXI MM interfaces on cell.
# @param cell the object whose interfaces shall be returned
# @parma mode filters interfaces by mode (default: Master)
......@@ -543,6 +573,31 @@ namespace eval tapasco {
return [get_bd_intf_pins -of_objects $cell -filter "VLNV =~ xilinx.com:interface:aximm_rtl:* && MODE == $mode"]
}
# Returns the given property of a given AXI MM interface.
# Will raise an error, if none or conflicting values are found.
# @param name of property
# @param intf interface pin to get property for
# @return value of property
proc get_aximm_property {property intf} {
set dw [get_property $property $intf]
if {$dw == {}} {
set nets [get_bd_intf_nets -hierarchical -boundary_type lower -of_objects $intf]
set srcs [get_bd_intf_pins -of_objects $nets -filter "$property != {}"]
if {[llength $srcs] == 0} {
error "could not find a connected interface pin where $property is set"
} else {
set dws {}
foreach s $srcs { lappend dws [get_property $property $s] }
if {[llength $dws] > 1} {
error "found conflicting values for $property @ $intf: $dws"
}
return [lindex $dws 0]
}
} else {
return $dw
}
}
# Returns a key-value list of frequencies in the design.
proc get_frequencies {} {
return [list "host" [get_host_frequency] "design" [get_design_frequency] "memory" [get_mem_frequency]]
......
# create a dictionary of compatible VLNVs
dict set stdcomps axi_ic vlnv "xilinx.com:ip:axi_interconnect:2.1"
dict set stdcomps ps vlnv "xilinx.com:ip:processing_system7:5.5"
dict set stdcomps ps_bfm vlnv "xilinx.com:ip:processing_system7_bfm:2.0"
dict set stdcomps axi_irqc vlnv "xilinx.com:ip:axi_intc:4.1"
dict set stdcomps axi_cache vlnv "xilinx.com:ip:system_cache:3.0"
dict set stdcomps xlconcat vlnv "xilinx.com:ip:xlconcat:2.1"
dict set stdcomps xlslice vlnv "xilinx.com:ip:xlslice:1.0"
dict set stdcomps xlconst vlnv "xilinx.com:ip:xlconstant:1.1"
dict set stdcomps rst_gen vlnv "xilinx.com:ip:proc_sys_reset:5.0"
dict set stdcomps proto_conv vlnv "xilinx.com:ip:axi_protocol_converter:2.1"
dict set stdcomps bincnt vlnv "xilinx.com:ip:c_counter_binary:12.0"
dict set stdcomps dualdma vlnv "esa.informatik.tu-darmstadt.de:user:dual_dma:1.4"
dict set stdcomps oled_ctrl vlnv "esa.cs.tu-darmstadt.de:user:oled_pc:1.0"
dict set stdcomps mm_to_lite vlnv "esa.cs.tu-darmstadt.de:user:mm_to_lite:1.0"
dict set stdcomps system_cache vlnv "xilinx.com:ip:system_cache:3.1"
dict set stdcomps mig_core vlnv "xilinx.com:ip:mig_7series:4.0"
dict set stdcomps axi_pcie3_0 vlnv "xilinx.com:ip:axi_pcie3:2.1"
dict set stdcomps tapasco_status vlnv "esa.cs.tu-darmstadt.de:user:tapasco_status:1.1"
dict set stdcomps clk_wiz "xilinx.com:ip:clk_wiz:5.3"
dict set stdcomps msix_intr_ctrl vlnv "esa.informatik.tu-darmstadt.de:user:MSIXIntrCtrl:1.0"
dict set stdcomps axi_reg_slice vlnv "xilinx.com:ip:axi_register_slice:2.1"
dict set stdcomps dwidth_conv vlnv "xilinx.com:ip:axi_dwidth_converter:2.1"
# create a dictionary of compatible VLNVs
dict set stdcomps axi_ic vlnv "xilinx.com:ip:axi_interconnect:2.1"
dict set stdcomps ps vlnv "xilinx.com:ip:processing_system7:5.5"
dict set stdcomps ps_bfm vlnv "xilinx.com:ip:processing_system7_bfm:2.0"
dict set stdcomps axi_irqc vlnv "xilinx.com:ip:axi_intc:4.1"
dict set stdcomps axi_cache vlnv "xilinx.com:ip:system_cache:3.0"
dict set stdcomps xlconcat vlnv "xilinx.com:ip:xlconcat:2.1"
dict set stdcomps xlslice vlnv "xilinx.com:ip:xlslice:1.0"
dict set stdcomps xlconst vlnv "xilinx.com:ip:xlconstant:1.1"
dict set stdcomps rst_gen vlnv "xilinx.com:ip:proc_sys_reset:5.0"
dict set stdcomps proto_conv vlnv "xilinx.com:ip:axi_protocol_converter:2.1"
dict set stdcomps bincnt vlnv "xilinx.com:ip:c_counter_binary:12.0"
dict set stdcomps dualdma vlnv "esa.informatik.tu-darmstadt.de:user:dual_dma:1.5"
dict set stdcomps oled_ctrl vlnv "esa.cs.tu-darmstadt.de:user:oled_pc:1.0"
dict set stdcomps mm_to_lite vlnv "esa.cs.tu-darmstadt.de:user:mm_to_lite:1.0"
dict set stdcomps system_cache vlnv "xilinx.com:ip:system_cache:3.1"
dict set stdcomps mig_core vlnv "xilinx.com:ip:mig_7series:4.0"
dict set stdcomps axi_pcie3_0 vlnv "xilinx.com:ip:axi_pcie3:3.0"
dict set stdcomps tapasco_status vlnv "esa.cs.tu-darmstadt.de:user:tapasco_status:1.1"
dict set stdcomps clk_wiz "xilinx.com:ip:clk_wiz:5.3"
dict set stdcomps msix_intr_ctrl vlnv "esa.informatik.tu-darmstadt.de:user:MSIXIntrCtrl:1.0"
dict set stdcomps axi_reg_slice vlnv "xilinx.com:ip:axi_register_slice:2.1"
dict set stdcomps dwidth_conv vlnv "xilinx.com:ip:axi_dwidth_converter:2.1"
......@@ -23,3 +23,4 @@ dict set stdcomps clk_wiz "xilinx.com:ip:clk_wiz:5.3"
dict set stdcomps msix_intr_ctrl vlnv "esa.informatik.tu-darmstadt.de:user:MSIXIntrCtrl:1.0"
dict set stdcomps axi_reg_slice vlnv "xilinx.com:ip:axi_register_slice:2.1"
dict set stdcomps dwidth_conv vlnv "xilinx.com:ip:axi_dwidth_converter:2.1"
dict set stdcomps system_ila vlnv "xilinx.com:ip:system_ila:1.0"
......@@ -21,3 +21,4 @@ dict set stdcomps clk_wiz "xilinx.com:ip:clk_wiz:5.4"
dict set stdcomps msix_intr_ctrl vlnv "esa.informatik.tu-darmstadt.de:user:MSIXIntrCtrl:1.0"
dict set stdcomps axi_reg_slice vlnv "xilinx.com:ip:axi_register_slice:2.1"
dict set stdcomps dwidth_conv vlnv "xilinx.com:ip:axi_dwidth_converter:2.1"
dict set stdcomps system_ila vlnv "xilinx.com:ip:system_ila:1.0"
......@@ -24,4 +24,5 @@ dict set stdcomps clk_wiz "xilinx.com:ip:clk_wiz:5.4"
dict set stdcomps msix_intr_ctrl vlnv "esa.informatik.tu-darmstadt.de:user:MSIXIntrCtrl:1.0"
dict set stdcomps axi_reg_slice vlnv "xilinx.com:ip:axi_register_slice:2.1"
dict set stdcomps dwidth_conv vlnv "xilinx.com:ip:axi_dwidth_converter:2.1"
dict set stdcomps util_vector_logic vlnv "xilinx.com:ip:util_vector_logic:2.0"
\ No newline at end of file
dict set stdcomps util_vector_logic vlnv "xilinx.com:ip:util_vector_logic:2.0"
dict set stdcomps system_ila vlnv "xilinx.com:ip:system_ila:1.0"
# Makefile to build the ffLink module, which can be loaded with 'sudo insmod ffLink.ko' afterwards
# make should not be run as root, otherwise generated files cannot be removed correctly
# Name of Kernel module
# Name of Kernel module
obj-m := ffLink.o
# composition of files needed to compile
......@@ -35,5 +35,5 @@ ccflags-y := $(COMPILEFLAGS) $(DEBUGFLAGS)
all:
#@ KCFLAGS+="$(COMPILEFLAGS) $(DEBUGFLAGS)" make -C $(LINUX_HOME) M=$(PWD) modules
@ make -C $(LINUX_HOME) M=$(PWD) modules
clean:
clean:
@ make -C $(LINUX_HOME) M=$(PWD) clean
......@@ -33,6 +33,15 @@
static struct pci_data_struct pci_data;
#if LINUX_VERSION_CODE < KERNEL_VERSION(4,8,0)
static struct msix_entry msix_entries[REQUIRED_INTERRUPTS];
u32 pci_irq_vector(struct pci_dev *pdev, int c) {
return msix_entries[c].vector;
}
#endif
/******************************************************************************/
/**
......@@ -307,10 +316,17 @@ static int claim_msi(struct pci_dev *pdev)
for (i = 0; i < REQUIRED_INTERRUPTS; i++) {
pci_data.irq_mapping[i] = -1;
#if LINUX_VERSION_CODE < KERNEL_VERSION(4,8,0)
msix_entries[i].entry = i;
#endif
}
#if LINUX_VERSION_CODE < KERNEL_VERSION(4,8,0)
err = pci_enable_msix_range(pdev, msix_entries, REQUIRED_INTERRUPTS, REQUIRED_INTERRUPTS);
#else
/* set up MSI interrupt vector to max size */
err = pci_alloc_irq_vectors(pdev, REQUIRED_INTERRUPTS, REQUIRED_INTERRUPTS, PCI_IRQ_MSIX);
#endif
if (err <= 0) {
fflink_warn("Cannot set MSI vector (%d)\n", err);
......@@ -333,7 +349,11 @@ static int claim_msi(struct pci_dev *pdev)
error_pci_req_irq:
free_irqs(pdev);
#if LINUX_VERSION_CODE < KERNEL_VERSION(4,8,0)
pci_disable_msix(pdev);
#else
pci_free_irq_vectors(pdev);
#endif
error_no_msi:
return -ENOSPC;
}
......@@ -504,7 +524,11 @@ static void fflink_pci_remove(struct pci_dev *pdev)
fflink_info("Unload pci-device\n");
free_irqs(pdev);
#if LINUX_VERSION_CODE < KERNEL_VERSION(4,8,0)
pci_disable_msix(pdev);
#else
pci_free_irq_vectors(pdev);
#endif
iounmap(pci_data.kvirt_addr_bar0);
......
......@@ -62,7 +62,6 @@
#include "common/device_user.h"
#include "common/dma_ctrl.h"
#include "common/device_pcie.h"
/******************************************************************************/
#define FFLINK_PCI_NAME "FFLINK_PCI_DRIVER"
......
set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVCMOS33} [get_ports sys_clk]
create_clock -period 8.000 -name sys_clk_pin -waveform {0.000 4.000} -add [get_ports sys_clk]
......@@ -25,10 +25,8 @@ namespace eval clock_constraint {
# Constraints the input pins called 'sys_clk'
proc create_clock_constraint {} {
puts "clock_constraint: setting sys_clk constraint to 125 MHz, 50% duty cycle"
set clk [get_ports "sys_clk"]
set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } $clk
create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} $clk
read_xdc -unmanaged "$::env(TAPASCO_HOME)/platform/pynq/plugins/clock.xdc"
}
}
tapasco::register_plugin "platform::clock_constraint::create_clock_constraint" "post-synth"
tapasco::register_plugin "platform::clock_constraint::create_clock_constraint" "pre-wrapper"
#
# Copyright (C) 2017 Jens Korinth, TU Darmstadt
#
# This file is part of Tapasco (TPC).
#
# Tapasco is free software: you can redistribute it and/or modify
# it under the terms of the GNU Lesser General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# Tapasco is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU Lesser General Public License for more details.
#
# You should have received a copy of the GNU Lesser General Public License
# along with Tapasco. If not, see <http://www.gnu.org/licenses/>.
#
# @file leds.tcl
# @brief Plugin to map general purpose LEDs on-board to signals.
# @author J. Korinth, TU Darmstadt (jk@esa.cs.tu-darmstadt.de)
#
namespace eval leds {
set default_led_pins [list "/uArch/irq_0" "/InterruptControl/irq_out"]
proc get_width {input} {
set l [get_property LEFT $input]
set r [get_property RIGHT $input]
return [expr $l - $r + 1]
}
proc calc_total_width {inputs} {
set w 0
foreach i $inputs { incr w [get_width $i] }
return $w
}
proc split_input {input} {
set width [get_width $input]
set name [get_property NAME $input]
set pins {}
set old_inst [current_bd_instance .]
set cell [create_bd_cell -type hier "${name}_splitter"]
current_bd_instance $cell
for {set i 0} {$i < $width} {incr i} {
set slice [tapasco::createSlice ${name}_$i $width $i]
connect_bd_net $input [get_bd_pins -of_objects $slice -filter { DIR == I }]
lappend pins [get_bd_pins -of_objects $slice -filter { DIR == O }]
}
current_bd_instance $old_inst
return $pins
}
proc get_led_inputs {inputs} {
set rlist [list]
foreach i $inputs {
set pin [get_bd_pins $i]
set width [get_width $pin]
puts " LED: $pin \[width: $width\]"
if {$width > 1} {
set split_pins [split_input $pin]
foreach p $split_pins { lappend rlist $p }
} else {
lappend rlist [get_bd_pins $pin]
}
}
set total_width [calc_total_width $rlist]
if {$total_width < 6} {
# create tie-off constant zero
set zero [tapasco::createConstant zero 1 0]
set pin [get_bd_pins -of_objects $zero -filter {DIR == "O"}]
for {set i $total_width} {$i < 6} {incr i} { lappend rlist $pin }
}
if {$total_width > 6} {
puts " WARNING: can only connect up to 6 LEDs, additional inputs will be discarded"
}
return $rlist
}
proc create_led_core {{name "gp_led"} {inputs [list]}} {
variable default_led_pins
puts "Creating LED core ..."