Commit cea36203 authored by David Volz's avatar David Volz
Browse files

check correct length

parent ddf7ab7f
Pipeline #2558 passed with stages
in 209 minutes and 45 seconds
......@@ -41,7 +41,7 @@ namespace eval arch {
set mem_slaves 0
foreach seg $reg_segs { if {[get_property MODE [get_bd_intf_pins -of_objects $seg]] == "Slave"} { incr reg_slaves } }
foreach seg $mem_segs { if {[get_property MODE [get_bd_intf_pins -of_objects $seg]] == "Slave"} { incr mem_slaves } }
if {[llength $reg_slaves] <= 1 && [llength $mem_slaves] <= 1} {
if {$reg_slaves <= 1 && $mem_slaves <= 1} {
puts " processing $pe registers ..."
for {set i 0} {$i < [llength $reg_segs]} {incr i} {
set seg [lindex $reg_segs $i]
......
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