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Commit d03e38c3 authored by Jaco Hofmann's avatar Jaco Hofmann
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Fixes VCU118 support 

    - Uses shim layer to convert between "old" MSIx Interface and US+
    MSIx interface
    - Adding additional US+ devices should be rather simple now
parent 6071f909
Pipeline #661 passed with stage
in 9 minutes and 27 seconds
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common/common_ip.tcl
View file @ d03e38c3
......@@ -12,6 +12,7 @@ dict set stdcomps rst_gen vlnv "xilinx.com:ip:proc_sys_reset:5.0"
dict set stdcomps proto_conv vlnv "xilinx.com:ip:axi_protocol_converter:2.1"
dict set stdcomps bincnt vlnv "xilinx.com:ip:c_counter_binary:12.0"
dict set stdcomps bluedma vlnv "esa.informatik.tu-darmstadt.de:user:BlueDMA:1.0"
dict set stdcomps msixusptrans vlnv "esa.informatik.tu-darmstadt.de:user:MSIxUSPTranslator:1.0"
dict set stdcomps oled_ctrl vlnv "esa.cs.tu-darmstadt.de:user:oled_pc:1.0"
dict set stdcomps mm_to_lite vlnv "esa.cs.tu-darmstadt.de:user:mm_to_lite:1.0"
dict set stdcomps system_cache vlnv "xilinx.com:ip:system_cache:3.1"
......
common/ip.tcl
View file @ d03e38c3
......@@ -294,6 +294,21 @@ namespace eval ::tapasco::ip {
return $inst
}
proc create_msixusptrans {name pcie} {
variable stdcomps
puts "Creating translator for US+ MSIx VLNV and connecting it to $pcie ..."
puts " VLNV: [dict get $stdcomps msixusptrans vlnv]"
set inst [create_bd_cell -type ip -vlnv [dict get $stdcomps msixusptrans vlnv] $name]
connect_bd_net [get_bd_pins $pcie/cfg_interrupt_msix_address] [get_bd_pins $inst/m_cfg_interrupt_msix_address]
connect_bd_net [get_bd_pins $pcie/cfg_interrupt_msix_data] [get_bd_pins $inst/m_cfg_interrupt_msix_data]
connect_bd_net [get_bd_pins $inst/m_cfg_interrupt_msix_int] [get_bd_pins $pcie/cfg_interrupt_msix_int]
connect_bd_net [get_bd_pins $pcie/cfg_interrupt_msix_enable] [get_bd_pins $inst/m_cfg_interrupt_msix_enable]
connect_bd_net [get_bd_pins $pcie/cfg_interrupt_msi_fail] [get_bd_pins $inst/m_cfg_interrupt_msix_fail]
connect_bd_net [get_bd_pins $inst/m_cfg_interrupt_msix_sent] [get_bd_pins $pcie/cfg_interrupt_msi_sent]
return $inst
}
# Instantiates an AXI System Cache.
# @param name Name of the instance.
proc create_axi_cache {name {num_ports 3} {size 262144} {num_sets 2}} {
......
common/ip/MSIxUSPTranslator/component.xml 0 → 100644
View file @ d03e38c3
<?xml version="1.0" encoding="UTF-8"?>
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>esa.informatik.tu-darmstadt.de</spirit:vendor>
<spirit:library>user</spirit:library>
<spirit:name>MSIxUSPTranslator</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
<spirit:name>fromMSIxController</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie3_cfg_msix" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie3_cfg_msix_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>fail</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_cfg_interrupt_msix_fail</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>int_vector</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_cfg_interrupt_msix_int</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>address</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_cfg_interrupt_msix_address</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>data</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_cfg_interrupt_msix_data</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>sent</spirit:name>
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<spirit:physicalPort>
<spirit:name>s_cfg_interrupt_msix_sent</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>enable</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_cfg_interrupt_msix_enable</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
</spirit:busInterface>
</spirit:busInterfaces>
<spirit:model>
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<spirit:view>
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
<spirit:displayName>Synthesis</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName>MSIxUSPTranslator</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
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<spirit:parameters>
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<spirit:view>
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
<spirit:displayName>Simulation</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName>MSIxUSPTranslator</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
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<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>fc56271c</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_xpgui</spirit:name>
<spirit:displayName>UI Layout</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
<spirit:fileSetRef>
<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
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<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>f92e9879</spirit:value>
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</spirit:view>
</spirit:views>
<spirit:ports>
<spirit:port>
<spirit:name>s_cfg_interrupt_msix_address</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">63</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
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<spirit:port>
<spirit:name>s_cfg_interrupt_msix_data</spirit:name>
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<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:port>
<spirit:name>s_cfg_interrupt_msix_enable</spirit:name>
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<spirit:port>
<spirit:name>m_cfg_interrupt_msix_fail</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
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<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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<spirit:port>
<spirit:name>m_cfg_interrupt_msix_sent</spirit:name>
<spirit:wire>
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<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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</spirit:ports>
</spirit:model>
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
<spirit:file>
<spirit:name>src/MSIxUSPTranslator.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>CHECKSUM_fc56271c</spirit:userFileType>
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</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
<spirit:file>
<spirit:name>src/MSIxUSPTranslator.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_xpgui_view_fileset</spirit:name>
<spirit:file>
<spirit:name>xgui/MSIxUSPTranslator_v1_0.tcl</spirit:name>
<spirit:fileType>tclSource</spirit:fileType>
<spirit:userFileType>CHECKSUM_f92e9879</spirit:userFileType>
<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
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</spirit:fileSet>
</spirit:fileSets>
<spirit:description>MSIxUSPTranslator</spirit:description>
<spirit:parameters>
<spirit:parameter>
<spirit:name>Component_Name</spirit:name>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">MSIxUSPTranslator_v1_0</spirit:value>
</spirit:parameter>
</spirit:parameters>
<spirit:vendorExtensions>
<xilinx:coreExtensions>
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<xilinx:family xilinx:lifeCycle="Pre-Production">kintexu</xilinx:family>
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<xilinx:taxonomies>
<xilinx:taxonomy>/UserIP</xilinx:taxonomy>
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<xilinx:displayName>MSIxUSPTranslator</xilinx:displayName>
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<xilinx:coreCreationDateTime>2018-10-29T11:14:52Z</xilinx:coreCreationDateTime>
<xilinx:tags>
<xilinx:tag xilinx:name="nopcore"/>
<xilinx:tag xilinx:name="esa.informatik.tu-darmstadt.de:user:MSIxUSPTranslator:1.0_ARCHIVE_LOCATION">/home/wimi/jah/projects/tapasco/tapasco_2018.2/common/ip/MSIxUSPTranslator</xilinx:tag>
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</spirit:vendorExtensions>
</spirit:component>
common/ip/MSIxUSPTranslator/src/MSIxUSPTranslator.v 0 → 100644
View file @ d03e38c3
module MSIxUSPTranslator(
input [63:0] s_cfg_interrupt_msix_address,
input [31:0] s_cfg_interrupt_msix_data,
input s_cfg_interrupt_msix_int,
output [3:0] s_cfg_interrupt_msix_enable,
output s_cfg_interrupt_msix_fail,
output s_cfg_interrupt_msix_sent,
output [63:0] m_cfg_interrupt_msix_address,
output [31:0] m_cfg_interrupt_msix_data,
output m_cfg_interrupt_msix_int,
input [3:0] m_cfg_interrupt_msix_enable,
input m_cfg_interrupt_msix_fail,
input m_cfg_interrupt_msix_sent
);
assign m_cfg_interrupt_msix_address = s_cfg_interrupt_msix_address;
assign m_cfg_interrupt_msix_data = s_cfg_interrupt_msix_data;
assign m_cfg_interrupt_msix_int = s_cfg_interrupt_msix_int;
assign s_cfg_interrupt_msix_enable = m_cfg_interrupt_msix_enable;
assign s_cfg_interrupt_msix_fail = m_cfg_interrupt_msix_fail;
assign s_cfg_interrupt_msix_sent = m_cfg_interrupt_msix_sent;
endmodule
common/ip/MSIxUSPTranslator/xgui/MSIxUSPTranslator_v1_0.tcl 0 → 100644
View file @ d03e38c3
# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
ipgui::add_page $IPINST -name "Page 0"
}
common/ip/PCIeBridgeToLite/component.xml
View file @ d03e38c3
......@@ -611,7 +611,7 @@
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<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>e11af023</spirit:value>
<spirit:value>dac150e9</spirit:value>
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</spirit:view>
......@@ -627,7 +627,7 @@
<spirit:parameters>
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<spirit:value>e11af023</spirit:value>
<spirit:value>dac150e9</spirit:value>
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......@@ -707,7 +707,7 @@
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......@@ -945,7 +945,7 @@
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......@@ -1051,7 +1051,7 @@
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......@@ -1407,7 +1407,7 @@
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......@@ -1762,7 +1762,7 @@
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<spirit:name>src/mkPCIeBridgeToLite.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
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......@@ -1826,18 +1826,18 @@
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<xilinx:definitionSource>package_project</xilinx:definitionSource>
<xilinx:coreRevision>1</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2018-08-16T14:01:25Z</xilinx:coreCreationDateTime>
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<xilinx:checksum xilinx:scope="parameters" xilinx:value="9f0be055"/>
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......
common/ip/PCIeBridgeToLite/src/mkPCIeBridgeToLite.v
View file @ d03e38c3
//
// Generated by Bluespec Compiler, version 2017.07.A (build 1da80f1, 2017-07-21)
//
// On Thu Aug 16 16:01:05 CEST 2018
// On Fri Oct 26 16:52:53 CEST 2018
//
//
// Ports:
// Name I/O size props
// S_AXI_arready O 1 reg
// S_AXI_rvalid O 1 reg
// S_AXI_rid O 3
// S_AXI_rid O 4
// S_AXI_rdata O 256
// S_AXI_rresp O 2
// S_AXI_rlast O 1
......@@ -17,7 +17,7 @@
// S_AXI_wready O 1 reg
// S_AXI_bvalid O 1 reg
// S_AXI_bresp O 2
// S_AXI_bid O 3
// S_AXI_bid O 4
// S_AXI_buser O 1
// M_AXI_arvalid O 1 reg
// M_AXI_araddr O 64
......@@ -33,7 +33,7 @@
// S_AXI_ACLK I 1 clock
// S_AXI_ARESETN I 1 reset
// S_AXI_arvalid I 1
// S_AXI_arid I 3
// S_AXI_arid I 4
// S_AXI_araddr I 64
// S_AXI_arlen I 8
// S_AXI_arsize I 3
......@@ -46,7 +46,7 @@
// S_AXI_aruser I 1
// S_AXI_rready I 1
// S_AXI_awvalid I 1
// S_AXI_awid I 3
// S_AXI_awid I 4
// S_AXI_awaddr I 64
// S_AXI_awlen I 8
// S_AXI_awsize I 3
......@@ -204,7 +204,7 @@ module mkPCIeBridgeToLite(S_AXI_ACLK,
output S_AXI_arready;
// action method s_rd_parchannel
input [2 : 0] S_AXI_arid;
input [3 : 0] S_AXI_arid;
input [63 : 0] S_AXI_araddr;
input [7 : 0] S_AXI_arlen;
input [2 : 0] S_AXI_arsize;
......@@ -223,7 +223,7 @@ module mkPCIeBridgeToLite(S_AXI_ACLK,
output S_AXI_rvalid;
// value method s_rd_rid
output [2 : 0] S_AXI_rid;
output [3 : 0] S_AXI_rid;
// value method s_rd_rdata
output [255 : 0] S_AXI_rdata;
......@@ -244,7 +244,7 @@ module mkPCIeBridgeToLite(S_AXI_ACLK,
input S_AXI_awvalid;
// action method s_wr_pawchannel
input [2 : 0] S_AXI_awid;
input [3 : 0] S_AXI_awid;
input [63 : 0] S_AXI_awaddr;
input [7 : 0] S_AXI_awlen;
input [2 : 0] S_AXI_awsize;
......@@ -278,7 +278,7 @@ module mkPCIeBridgeToLite(S_AXI_ACLK,
output [1 : 0] S_AXI_bresp;
// value method s_wr_bid
output [2 : 0] S_AXI_bid;
output [3 : 0] S_AXI_bid;
// value method s_wr_buser
output S_AXI_buser;
......@@ -344,7 +344,8 @@ module mkPCIeBridgeToLite(S_AXI_ACLK,
wire [255 : 0] S_AXI_rdata;
wire [63 : 0] M_AXI_araddr, M_AXI_awaddr, M_AXI_wdata;
wire [7 : 0] M_AXI_wstrb;
wire [2 : 0] M_AXI_arprot, M_AXI_awprot, S_AXI_bid, S_AXI_rid;
wire [3 : 0] S_AXI_bid, S_AXI_rid;
wire [2 : 0] M_AXI_arprot, M_AXI_awprot;
wire [1 : 0] S_AXI_bresp, S_AXI_rresp;
wire M_AXI_arvalid,
M_AXI_awvalid,
......@@ -362,7 +363,7 @@ module mkPCIeBridgeToLite(S_AXI_ACLK,
// inlined wires
wire [289 : 0] writeSlave_arinpkg_data$wget;
wire [96 : 0] readSlave_arinpkg$wget, writeSlave_arinpkg_addr$wget;
wire [97 : 0] readSlave_arinpkg$wget, writeSlave_arinpkg_addr$wget;