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tapasco
tapasco
Commits
d81c7aa2
Commit
d81c7aa2
authored
May 17, 2019
by
Jaco Hofmann
Browse files
Revert "Move to AXI based interrupts"
This reverts commit
4f8a6580
.
parent
4f8a6580
Changes
4
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common/ip/MSIXIntrCtrl/component.xml
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d81c7aa2
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common/ip/MSIXIntrCtrl/src/FIFO1.v
deleted
100644 → 0
View file @
4f8a6580
// Copyright (c) 2000-2012 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision$
// $Date$
`ifdef
BSV_ASSIGNMENT_DELAY
`else
`define
BSV_ASSIGNMENT_DELAY
`endif
`ifdef
BSV_POSITIVE_RESET
`define
BSV_RESET_VALUE 1
'
b1
`define
BSV_RESET_EDGE posedge
`else
`define
BSV_RESET_VALUE 1
'
b0
`define
BSV_RESET_EDGE negedge
`endif
`ifdef
BSV_ASYNC_RESET
`define
BSV_ARESET_EDGE_META or
`
BSV_RESET_EDGE RST
`else
`define
BSV_ARESET_EDGE_META
`endif
`ifdef
BSV_RESET_FIFO_HEAD
`define
BSV_ARESET_EDGE_HEAD
`
BSV_ARESET_EDGE_META
`else
`define
BSV_ARESET_EDGE_HEAD
`endif
// Depth 1 FIFO
module
FIFO1
(
CLK
,
RST
,
D_IN
,
ENQ
,
FULL_N
,
D_OUT
,
DEQ
,
EMPTY_N
,
CLR
);
parameter
width
=
1
;
parameter
guarded
=
1
;
input
CLK
;
input
RST
;
input
[
width
-
1
:
0
]
D_IN
;
input
ENQ
;
input
DEQ
;
input
CLR
;
output
FULL_N
;
output
[
width
-
1
:
0
]
D_OUT
;
output
EMPTY_N
;
reg
[
width
-
1
:
0
]
D_OUT
;
reg
empty_reg
;
assign
EMPTY_N
=
empty_reg
;
`ifdef
BSV_NO_INITIAL_BLOCKS
`else
// not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin
D_OUT
=
{
((
width
+
1
)
/
2
)
{
2'b10
}}
;
empty_reg
=
1'b0
;
end
// initial begin
// synopsys translate_on
`endif
// BSV_NO_INITIAL_BLOCKS
assign
FULL_N
=
!
empty_reg
;
always
@
(
posedge
CLK
`BSV_ARESET_EDGE_META
)
begin
if
(
RST
==
`BSV_RESET_VALUE
)
begin
empty_reg
<=
`BSV_ASSIGNMENT_DELAY
1'b0
;
end
// if (RST == `BSV_RESET_VALUE)
else
begin
if
(
CLR
)
begin
empty_reg
<=
`BSV_ASSIGNMENT_DELAY
1'b0
;
end
// if (CLR)
else
if
(
ENQ
)
begin
empty_reg
<=
`BSV_ASSIGNMENT_DELAY
1'b1
;
end
// if (ENQ)
else
if
(
DEQ
)
begin
empty_reg
<=
`BSV_ASSIGNMENT_DELAY
1'b0
;
end
// if (DEQ)
end
// else: !if(RST == `BSV_RESET_VALUE)
end
// always@ (posedge CLK or `BSV_RESET_EDGE RST)
always
@
(
posedge
CLK
`BSV_ARESET_EDGE_HEAD
)
begin
`ifdef
BSV_RESET_FIFO_HEAD
if
(
RST
==
`BSV_RESET_VALUE
)
begin
D_OUT
<=
`BSV_ASSIGNMENT_DELAY
{
width
{
1'b0
}}
;
end
else
`endif
begin
if
(
ENQ
)
D_OUT
<=
`BSV_ASSIGNMENT_DELAY
D_IN
;
end
// else: !if(RST == `BSV_RESET_VALUE)
end
// always@ (posedge CLK or `BSV_RESET_EDGE RST)
// synopsys translate_off
always
@
(
posedge
CLK
)
begin:
error_checks
reg
deqerror
,
enqerror
;
deqerror
=
0
;
enqerror
=
0
;
if
(
RST
==
!
`BSV_RESET_VALUE
)
begin
if
(
!
empty_reg
&&
DEQ
)
begin
deqerror
=
1
;
$
display
(
"Warning: FIFO1: %m -- Dequeuing from empty fifo"
)
;
end
if
(
!
FULL_N
&&
ENQ
&&
(
!
DEQ
||
guarded
)
)
begin
enqerror
=
1
;
$
display
(
"Warning: FIFO1: %m -- Enqueuing to a full fifo"
)
;
end
end
// if (RST == ! `BSV_RESET_VALUE)
end
// synopsys translate_on
endmodule
common/ip/MSIXIntrCtrl/src/mkMSIXIntrCtrl.v
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d81c7aa2
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platform/pcie/pcie_base.tcl
View file @
d81c7aa2
...
...
@@ -109,7 +109,7 @@
puts
"Connecting
[
llength $irqs
]
interrupts .."
# create hierarchical ports
set s_axi
[
create_bd_intf_pin -mode Slave -vlnv
[
tapasco::ip::get_vlnv
"aximm_intf"
]
"S_INTC"
]
set msix_interface
[
create_bd_intf_pin -mode Master -vlnv
[
tapasco::ip::get_vlnv
"aximm_intf"
]
"M_MSIX"
]
set msix_interface
[
create_bd_intf_pin -mode Master -vlnv
xilinx.com:interface:pcie3_cfg_msix_rtl:1.0
"M_MSIX"
]
set aclk
[
tapasco::subsystem::get_port
"host"
"clk"
]
set p_aresetn
[
tapasco::subsystem::get_port
"host"
"rst"
"peripheral"
"resetn"
]
set design_aclk
[
tapasco::subsystem::get_port
"design"
"clk"
]
...
...
@@ -126,7 +126,7 @@
set msix_intr_ctrl
[
tapasco::ip::create_msix_intr_ctrl
"msix_intr_ctrl"
]
connect_bd_net
[
get_bd_pin -of_objects $irq_concat_ss -filter
{
NAME ==
"dout"
}]
[
get_bd_pin -of_objects $msix_intr_ctrl -filter
{
NAME ==
"interrupt_pcie"
}]
connect_bd_intf_net $msix_interface
[
get_bd_intf_pins msix_intr_ctrl/
M_AXI
]
connect_bd_intf_net $msix_interface
[
get_bd_intf_pins msix_intr_ctrl/
msix
]
connect_bd_net $dma_irq_read
[
get_bd_pin -of_objects $irq_concat_ss -filter
{
NAME ==
"In0"
}]
connect_bd_net $dma_irq_write
[
get_bd_pin -of_objects $irq_concat_ss -filter
{
NAME ==
"In1"
}]
...
...
@@ -293,11 +293,18 @@
set m_dma
[
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0
"M_DMA"
]
set pcie_aclk
[
create_bd_pin -type
"clk"
-dir
"O"
"pcie_aclk"
]
set pcie_aresetn
[
create_bd_pin -type
"rst"
-dir
"O"
"pcie_aresetn"
]
set msix_interface
[
create_bd_intf_pin -mode Slave -vlnv
[
tapasco::ip::get_vlnv
"aximm_intf"
]
"S_MSIX"
]
set msix_interface
[
create_bd_intf_pin -mode Slave -vlnv
xilinx.com:interface:pcie3_cfg_msix_rtl:1.0
"S_MSIX"
]
# create instances of cores: PCIe core, mm_to_lite
set pcie
[
create_pcie_core
]
set trans
[
get_bd_cells -filter
{
NAME ==
"MSIxTranslator"
}]
if
{
$trans !=
""
}
{
connect_bd_intf_net $msix_interface
[
get_bd_intf_pins $trans/fromMSIxController
]
}
else
{
connect_bd_intf_net $msix_interface
[
get_bd_intf_pins $pcie/pcie_cfg_msix
]
}
set out_ic
[
tapasco::ip::create_axi_sc
"out_ic"
1 4
]
tapasco::ip::connect_sc_default_clocks $out_ic
"design"
...
...
@@ -326,7 +333,6 @@
tapasco::ip::connect_sc_default_clocks $in_ic
"host"
connect_bd_intf_net
[
get_bd_intf_pins S_HOST
]
[
get_bd_intf_pins $in_ic/S00_AXI
]
connect_bd_intf_net $msix_interface
[
get_bd_intf_pins $in_ic/S01_AXI
]
connect_bd_intf_net
[
get_bd_intf_pins -of_object $in_ic -filter
{
MODE == Master
}]
\
[
get_bd_intf_pins -regexp $pcie/S_AXI
(
_B
)
?
]
...
...
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