Commit da655ea7 authored by Jens Korinth's avatar Jens Korinth
Browse files

Implement spec tests for RTL behavior

* re-used generic test from RegisterFile
* status configuration is generated by spec gens
parent 5533df8a
......@@ -25,7 +25,7 @@ object Builder {
private def makeConfiguration(status: Status): RegisterFile.Configuration = RegisterFile.Configuration(
def makeConfiguration(status: Status): RegisterFile.Configuration = RegisterFile.Configuration(
regs = (Seq[(Long, ControlRegister)](
0x00L -> new ConstantRegister(Some("Magic ID"), value = BigInt("E5AE1337", 16)),
0x04L -> new ConstantRegister(Some("Int Count"), value = BigInt(status.interruptControllers)),
package de.tu_darmstadt.cs.esa.tapasco.tapasco_status
import chisel.axi._, chisel.axi.axi4lite._
import chisel.miscutils.Logging
import generators._
import chisel3.iotesters.ChiselFlatSpec
import org.scalatest.prop.Checkers
import org.scalacheck.Prop._
class StatusSpec extends ChiselFlatSpec with Checkers {
implicit val axi = Axi4Lite.Configuration(dataWidth = Axi4Lite.Width32, addrWidth = AddrWidth(12))
implicit val llv = Logging.Level.Info
val chiselArgs = Array("--fint-write-vcd")
behavior of "tapasco_status"
it should "behave correctly in generic test" in check(forAllNoShrink(genStatus) { status =>
val regs = Builder.makeConfiguration(status).regs map { case (addr, reg) => (addr, Some(reg)) }
RegisterFileSpec.genericTest(chiselArgs, axi.dataWidth, regs)
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