Commit df0710b6 authored by Jens Korinth's avatar Jens Korinth
Browse files

Merged chisel-miscutils

Merge commit 'c60f21734856c5828fd574bffe7c6e31acf1c942'
parents 357a3810 dc850c61
......@@ -2,6 +2,13 @@ package chisel.miscutils
import chisel3._
import chisel3.util._
object DataWidthConverter {
class IO(inWidth: Int, outWidth: Int) extends Bundle {
val inq = Flipped(Decoupled(UInt(inWidth.W)))
val deq = Decoupled(UInt(outWidth.W))
}
}
/**
* DataWidthConverter converts the data width of a Queue.
* Output is provided via a Queue, with increased or decreased
......@@ -17,7 +24,8 @@ import chisel3.util._
**/
class DataWidthConverter(val inWidth: Int,
val outWidth: Int,
val littleEndian: Boolean = true) extends Module {
val littleEndian: Boolean = true)
(implicit logLevel: Logging.Level) extends Module with Logging {
require (inWidth > 0, "inWidth must be > 0")
require (outWidth > 0, "inWidth must be > 0")
require (inWidth != outWidth, "inWidth (%d) must be different from outWidth (%d)"
......@@ -26,10 +34,9 @@ class DataWidthConverter(val inWidth: Int,
"inWidth (%d) and outWidth (%d) must be integer multiples of each other"
.format(inWidth, outWidth))
val io = IO(new Bundle {
val inq = Flipped(Decoupled(UInt(inWidth.W)))
val deq = Decoupled(UInt(outWidth.W))
})
cinfo(s"inWidth = $inWidth, outWidth = $outWidth, littleEndian = $littleEndian")
val io = IO(new DataWidthConverter.IO(inWidth, outWidth))
val ratio: Int = if (inWidth > outWidth) inWidth / outWidth else outWidth / inWidth
val d_w = if (inWidth > outWidth) inWidth else outWidth // data register width
......
......@@ -2,11 +2,13 @@ package chisel.miscutils
import chisel3._
import chisel3.util._
/**
* Interface for DecoupledDataSource.
**/
class DecoupledDataSourceIO[T <: Data](gen: T) extends Bundle {
val out = Decoupled(gen.cloneType)
object DecoupledDataSource {
/**
* Interface for DecoupledDataSource.
**/
class IO[T <: Data](gen: T) extends Bundle {
val out = Decoupled(gen.cloneType)
}
}
/**
......@@ -30,11 +32,11 @@ class DecoupledDataSource[T <: Data](gen: T,
if (repeat) "true" else "false", log2Ceil(if (repeat) size else size + 1)))
val ds = for (i <- 0 until size) yield data(i) // evaluate data to array
val io = IO(new DecoupledDataSourceIO(gen)) // interface
val io = IO(new DecoupledDataSource.IO(gen)) // interface
val i = Reg(UInt(log2Ceil(if (repeat) size else size + 1).W)) // index
val rom = Vec.tabulate(size)(n => ds(n)) // ROM with data
io.out.bits := rom(i) // current index data
io.out.valid := !reset && i < size.U // valid until exceeded
io.out.valid := !reset && (i < size.U) // valid until exceeded
when (reset) {
i := 0.U
}
......
......@@ -16,6 +16,11 @@ object SignalGenerator {
implicit def makeSignal(sd: (Boolean, Int)): Signal = Signal(sd._1, sd._2)
implicit def makeWaveform(ls: List[(Boolean, Int)]): Waveform = ls map makeSignal
class IO extends Bundle {
val v = Output(Bool())
val in = Input(Bool())
}
}
class SignalGenerator(val signals: SignalGenerator.Waveform,
......@@ -23,7 +28,7 @@ class SignalGenerator(val signals: SignalGenerator.Waveform,
require (signals.length > 0, "Waveform must not be empty.")
require (signals map (_.periods > 1) reduce (_&&_),
"All signals must have at least two clock cycles length.")
val io = IO(new Bundle { val v = Output(Bool()); val in = Input(Bool()) })
val io = IO(new SignalGenerator.IO)
val cnts_rom = Vec(signals map (n => (n.periods - 1).U))
val vals_rom = Vec(signals map (n => (n.value).B))
val cnt = Reg(UInt(log2Ceil(signals.max.periods).W))
......
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