Commit e8e1cf67 authored by Jens Korinth's avatar Jens Korinth
Browse files

Implement generators for ScalaCheck for AXI configurations

parent 7fa3b107
package chisel.axi.axi4
import chisel.axi.generators._
import org.scalacheck.{Arbitrary, Gen}
package object generators {
object Axi4 {
val configurationGen: Gen[chisel.axi.Axi4.Configuration] = for {
addrWidth <- addrWidthGen
dataWidth <- dataWidthGen
userWidth <- userWidthGen
idWidth <- idWidthGen
regionWidth <- regionWidthGen
hasQoS <- Arbitrary.arbBool.arbitrary
} yield chisel.axi.Axi4.Configuration(addrWidth, dataWidth, idWidth, userWidth, regionWidth, hasQoS)
}
object Axi4Lite {
val dataWidthGen: Gen[chisel.axi.Axi4Lite.DataWidth] = Gen.oneOf(
chisel.axi.Axi4Lite.Width32,
chisel.axi.Axi4Lite.Width64
)
val configurationGen: Gen[chisel.axi.Axi4Lite.Configuration] = for {
addrWidth <- addrWidthGen
dataWidth <- dataWidthGen
userWidth <- userWidthGen
regionWidth <- regionWidthGen
} yield chisel.axi.Axi4Lite.Configuration(addrWidth, dataWidth, userWidth, regionWidth)
}
}
package chisel.axiutils.axi4lite
import chisel.axiutils.generators._
package object generators {
}
package chisel.axi
import chisel.miscutils.generators._
import org.scalacheck._
package object generators {
val addrWidthGen: Gen[AddrWidth] = genLimited(1, 64) map (AddrWidth(_))
val dataWidthGen: Gen[DataWidth] = genLimited(1, 4096) map (DataWidth(_))
val userWidthGen: Gen[UserWidth] = Gen.frequency(
90 -> UserWidth(0),
10 -> (genLimited(1, 15) map (UserWidth(_)))
)
val idWidthGen: Gen[IdWidth] = genLimited(0, 15) map (IdWidth(_))
val regionWidthGen: Gen[RegionWidth] = genLimited(0, 4) map (RegionWidth(_))
}
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