Commit e8e3c677 authored by David Volz's avatar David Volz
Browse files

clarifying comment

parent 7e8f3137
Pipeline #2552 passed with stages
in 158 minutes and 45 seconds
......@@ -69,7 +69,10 @@ namespace eval arch {
}
}
} else {
# if there is more than one reg/mem interface, we assume that the user knows what they are doing and add them in the same order
# If there is more than one reg/mem interface, we add them in the same order as declared in the IP-XACT core.
# The current runtime uses the order to detect control-register-interface & memory-interface pairs.
# When a PE has multiple such interfaces, ordering them regs first, mems second leads to the runtime recognizing only one reg-memory pair.
# When using the same ordering as the IP-XACT core, the user can define which memory-interface belongs to a certain control-register-interface by ordering them accordingly.
puts " processing $pe registers and memories ..."
set all_segs [lsort [get_bd_addr_segs $pe/*]]
for {set i 0} {$i < [llength $all_segs]} {incr i} {
......
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