Commit f581c158 authored by Jens Korinth's avatar Jens Korinth
Browse files

Write FifoAxiAdapter specification

*  basic tests implemented
*  peekAt/pokeAt do not work; took a lot of time to figure out
*  need to implement a workaround using a serial interface
*  introduces its own problems, *sigh*
parent df0710b6
package chisel.axiutils package chisel.axiutils
import chisel.axiutils.axi4lite._ import chisel.axiutils.axi4lite._, chisel.axiutils.axi4._
import chisel.packaging._, chisel.packaging.CoreDefinition.root import chisel.packaging._, chisel.packaging.CoreDefinition.root
import chisel.miscutils.DecoupledDataSource, chisel.miscutils.Logging import chisel.miscutils.DecoupledDataSource, chisel.miscutils.Logging
import scala.sys.process._ import scala.sys.process._
......
...@@ -8,7 +8,10 @@ object Axi4 { ...@@ -8,7 +8,10 @@ object Axi4 {
val idWidth: IdWidth = IdWidth(1), val idWidth: IdWidth = IdWidth(1),
val userWidth: UserWidth = UserWidth(0), val userWidth: UserWidth = UserWidth(0),
val regionWidth: RegionWidth = RegionWidth(0), val regionWidth: RegionWidth = RegionWidth(0),
val hasQoS: Boolean = false) val hasQoS: Boolean = false) {
override def toString: String =
s"Axi4($addrWidth $dataWidth $idWidth $userWidth $regionWidth $hasQoS)"
}
object Configuration { object Configuration {
def apply(addrWidth: AddrWidth, def apply(addrWidth: AddrWidth,
......
package chisel.axiutils.axi4 package chisel.axiutils.axi4
import generators._, chisel.miscutils.generators._
import chisel.miscutils._
import chisel.axi._
import chisel3._
import chisel3.iotesters.{ChiselFlatSpec, Driver, PeekPokeTester} import chisel3.iotesters.{ChiselFlatSpec, Driver, PeekPokeTester}
import org.scalatest.prop.Checkers import org.scalatest.prop.Checkers
import org.scalacheck._, org.scalacheck.Prop._ import org.scalacheck._, org.scalacheck.Prop._
class FifoAxiAdapterTest(fifoDepth: Int, val data: Seq[BigInt], repeat: Boolean)
(implicit axi: Axi4.Configuration,
logLevel: Logging.Level) extends Module {
val m = Module(new FifoAxiAdapter(fifoDepth))
val src = Module(new DecoupledDataSource(UInt(axi.dataWidth), data.length, data map (_.U), repeat))
val dst = Module(new SlaveModel(SlaveModel.Configuration(readDelay = 0, writeDelay = 0)))
val io = IO(new Bundle {
val debug = dst.io.debug.cloneType
})
src.io.out <> m.io.enq
m.io.base := 0.U
m.io.maxi <> dst.io.saxi
dst.io.debug <> io.debug
}
class FifoAxiAdapterTester(m: FifoAxiAdapterTest) extends PeekPokeTester(m) {
implicit val tester = this
poke(m.io.debug.w, false)
poke(m.io.debug.r, false)
reset(10)
step(m.data.length * 50)
poke(m.io.debug.r, true)
0 until m.data.length foreach { i =>
poke(m.io.debug.ra, i)
step(1)
expect(m.io.debug.dout, m.data(i), s"wrong data at $i")
}
step(10)
}
class FifoAxiAdapterSpec extends ChiselFlatSpec with Checkers { class FifoAxiAdapterSpec extends ChiselFlatSpec with Checkers {
implicit val logLevel = Logging.Level.Info
behavior of "FifoAxiAdapter" behavior of "FifoAxiAdapter"
it should "say hello" in { it should "say hello" in {
check({ println("hello!"); true }) check({ println("hello!"); true })
} }
// it should "work with arbitrary configurations" it should "work with arbitrary configurations" in
check(forAll(axi4CfgGen, fifoDepthGen) { case (axi4, fd) =>
forAllNoShrink(dataGen(BitWidth(axi4.dataWidth.width)(1024))) { data =>
implicit val a = axi4
try {
Driver.execute(Array("--fint-write-vcd", "--target-dir", "test/axi4/FifoAxiAdapter"),
() => new FifoAxiAdapterTest(fd, data, false))
{ m => new FifoAxiAdapterTester(m) }
} catch { case t: Throwable =>
t.getStackTrace() foreach (println(_))
throw t
}
}})
} }
...@@ -6,8 +6,16 @@ import org.scalacheck._ ...@@ -6,8 +6,16 @@ import org.scalacheck._
package object generators { package object generators {
val axi4CfgGen: Gen[Axi4.Configuration] = for { val axi4CfgGen: Gen[Axi4.Configuration] = for {
aw <- bitWidthGen(64) aw <- bitWidthGen(64)
dw <- bitWidthGen(1024) dw <- bitWidthGen(128)
} yield Axi4.Configuration(addrWidth = AddrWidth(aw), dataWidth = DataWidth(dw)) } yield Axi4.Configuration(addrWidth = AddrWidth(aw), dataWidth = DataWidth(dw))
val fifoDepthGen: Gen[Limited[Int]] = genLimited(1, 16) val fifoDepthGen: Gen[Limited[Int]] = genLimited(1, 16)
def bitStringGen(width: BitWidth): Gen[String] =
Gen.buildableOfN[String, Char](width, Gen.oneOf('0', '1'))
def dataGen(width: BitWidth, minElems: Int = 1, maxElems: Int = 1024): Gen[Seq[BigInt]] = for {
n <- genLimited(minElems, maxElems)
d <- Gen.buildableOfN[Seq[BigInt], BigInt](n, bitStringGen(width) map (BigInt(_, 2)))
} yield d
} }
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