Commit f9148c81 authored by Jens Korinth's avatar Jens Korinth
Browse files

Squashed commit of the following:

commit d3245516
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jan 25 10:19:19 2018 +0100

    Closes #149 - Zedboard Synthesis fails for 2017.3 and 2017.4

    * improved sys clock detection by checking available interfaces via
      get_board_part_interfaces, instead of trying sys_diff_clock first
    * also removed second warning when get_bd_pins returns nothing
    * removed old, unused platform code

commit 9a0fb9b0
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jan 25 10:18:03 2018 +0100

    Use Arty-Z7-20 board file from Digilent for PyNQ

    * contains the manually set top.xdc directives
    * identical to Pynq, except for peripheral components

commit f6a25afc
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jan 25 10:16:28 2018 +0100

    Update board definition for zedboard

    * Digilent has newer def of ZedBoard, using that automatically now
    * imported via MYVIVADO / XILINX_PATH env vars

commit a29aa6cc
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jan 25 10:14:39 2018 +0100

    Fix minor bug in PS7 instantiation routine

commit c782eadc
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jan 25 10:13:58 2018 +0100

    Remove 2016.4 specific code from design.master.tcl.template
parent f873c47b
This diff is collapsed.
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<part_info part_name="xc7z020clg400-1">
<pins>
<pin index="0" name ="btns_4bits_tri_i_0" iostandard="LVCMOS33" loc="D19"/>
<pin index="1" name ="btns_4bits_tri_i_1" iostandard="LVCMOS33" loc="D20"/>
<pin index="2" name ="btns_4bits_tri_i_2" iostandard="LVCMOS33" loc="L20"/>
<pin index="3" name ="btns_4bits_tri_i_3" iostandard="LVCMOS33" loc="L19"/>
<pin index="4" name ="leds_4bits_tri_o_0" iostandard="LVCMOS33" loc="R14"/>
<pin index="5" name ="leds_4bits_tri_o_1" iostandard="LVCMOS33" loc="P14"/>
<pin index="6" name ="leds_4bits_tri_o_2" iostandard="LVCMOS33" loc="N16"/>
<pin index="7" name ="leds_4bits_tri_o_3" iostandard="LVCMOS33" loc="M14"/>
<pin index="8" name ="sws_2bits_tri_i_0" iostandard="LVCMOS33" loc="M20"/>
<pin index="9" name ="sws_2bits_tri_i_1" iostandard="LVCMOS33" loc="M19"/>
<pin index="10" name ="sys_clk" iostandard="LVCMOS33" loc="H16"/>
<pin index="11" name ="JA1" iostandard="LVCMOS33" loc="Y18"/>
<pin index="12" name ="JA2" iostandard="LVCMOS33" loc="Y19"/>
<pin index="13" name ="JA3" iostandard="LVCMOS33" loc="Y16"/>
<pin index="14" name ="JA4" iostandard="LVCMOS33" loc="Y17"/>
<pin index="15" name ="JA7" iostandard="LVCMOS33" loc="U18"/>
<pin index="16" name ="JA8" iostandard="LVCMOS33" loc="U19"/>
<pin index="17" name ="JA9" iostandard="LVCMOS33" loc="W18"/>
<pin index="18" name ="JA10" iostandard="LVCMOS33" loc="W19"/>
<pin index="19" name ="JB1" iostandard="LVCMOS33" loc="W14"/>
<pin index="20" name ="JB2" iostandard="LVCMOS33" loc="Y14"/>
<pin index="21" name ="JB3" iostandard="LVCMOS33" loc="T11"/>
<pin index="22" name ="JB4" iostandard="LVCMOS33" loc="T10"/>
<pin index="23" name ="JB7" iostandard="LVCMOS33" loc="V16"/>
<pin index="24" name ="JB8" iostandard="LVCMOS33" loc="W16"/>
<pin index="25" name ="JB9" iostandard="LVCMOS33" loc="V12"/>
<pin index="26" name ="JB10" iostandard="LVCMOS33" loc="W13"/>
<pin index="27" name ="i2c_scl_i" iostandard="LVCMOS33" loc="P16"/>
<pin index="28" name ="i2c_sda_i" iostandard="LVCMOS33" loc="P15"/>
<pin index="29" name ="rgb_led_tri_o_0" iostandard="LVCMOS33" loc="L15"/>
<pin index="30" name ="rgb_led_tri_o_1" iostandard="LVCMOS33" loc="G17"/>
<pin index="31" name ="rgb_led_tri_o_2" iostandard="LVCMOS33" loc="N15"/>
<pin index="32" name ="rgb_led_tri_o_3" iostandard="LVCMOS33" loc="G14"/>
<pin index="33" name ="rgb_led_tri_o_4" iostandard="LVCMOS33" loc="L14"/>
<pin index="34" name ="rgb_led_tri_o_5" iostandard="LVCMOS33" loc="M15"/>
<pin index="35" name ="shield_dp0_dp13_tri_i_0" iostandard="LVCMOS33" loc="T14"/>
<pin index="36" name ="shield_dp0_dp13_tri_i_1" iostandard="LVCMOS33" loc="U12"/>
<pin index="37" name ="shield_dp0_dp13_tri_i_2" iostandard="LVCMOS33" loc="U13"/>
<pin index="38" name ="shield_dp0_dp13_tri_i_3" iostandard="LVCMOS33" loc="V13"/>
<pin index="39" name ="shield_dp0_dp13_tri_i_4" iostandard="LVCMOS33" loc="V15"/>
<pin index="40" name ="shield_dp0_dp13_tri_i_5" iostandard="LVCMOS33" loc="T15"/>
<pin index="41" name ="shield_dp0_dp13_tri_i_6" iostandard="LVCMOS33" loc="R16"/>
<pin index="42" name ="shield_dp0_dp13_tri_i_7" iostandard="LVCMOS33" loc="U17"/>
<pin index="43" name ="shield_dp0_dp13_tri_i_8" iostandard="LVCMOS33" loc="V17"/>
<pin index="44" name ="shield_dp0_dp13_tri_i_9" iostandard="LVCMOS33" loc="V18"/>
<pin index="45" name ="shield_dp0_dp13_tri_i_10" iostandard="LVCMOS33" loc="F16"/>
<pin index="46" name ="shield_dp0_dp13_tri_i_11" iostandard="LVCMOS33" loc="R17"/>
<pin index="47" name ="shield_dp0_dp13_tri_i_12" iostandard="LVCMOS33" loc="P18"/>
<pin index="48" name ="shield_dp0_dp13_tri_i_13" iostandard="LVCMOS33" loc="N17"/>
<pin index="49" name ="shield_dp26_dp41_tri_i_0" iostandard="LVCMOS33" loc="U5"/>
<pin index="50" name ="shield_dp26_dp41_tri_i_1" iostandard="LVCMOS33" loc="V5"/>
<pin index="51" name ="shield_dp26_dp41_tri_i_2" iostandard="LVCMOS33" loc="V6"/>
<pin index="52" name ="shield_dp26_dp41_tri_i_3" iostandard="LVCMOS33" loc="U7"/>
<pin index="53" name ="shield_dp26_dp41_tri_i_4" iostandard="LVCMOS33" loc="V7"/>
<pin index="54" name ="shield_dp26_dp41_tri_i_5" iostandard="LVCMOS33" loc="U8"/>
<pin index="55" name ="shield_dp26_dp41_tri_i_6" iostandard="LVCMOS33" loc="V8"/>
<pin index="56" name ="shield_dp26_dp41_tri_i_7" iostandard="LVCMOS33" loc="V10"/>
<pin index="57" name ="shield_dp26_dp41_tri_i_8" iostandard="LVCMOS33" loc="W10"/>
<pin index="58" name ="shield_dp26_dp41_tri_i_9" iostandard="LVCMOS33" loc="W6"/>
<pin index="59" name ="shield_dp26_dp41_tri_i_10" iostandard="LVCMOS33" loc="Y6"/>
<pin index="60" name ="shield_dp26_dp41_tri_i_11" iostandard="LVCMOS33" loc="Y7"/>
<pin index="61" name ="shield_dp26_dp41_tri_i_12" iostandard="LVCMOS33" loc="W8"/>
<pin index="62" name ="shield_dp26_dp41_tri_i_13" iostandard="LVCMOS33" loc="Y8"/>
<pin index="63" name ="shield_dp26_dp41_tri_i_14" iostandard="LVCMOS33" loc="W9"/>
<pin index="64" name ="shield_dp26_dp41_tri_i_15" iostandard="LVCMOS33" loc="Y9"/>
<pin index="65" name ="spi_miso_i" iostandard="LVCMOS33" loc="W15"/>
<pin index="66" name ="spi_mosi_i" iostandard="LVCMOS33" loc="T12"/>
<pin index="67" name ="spi_sclk_i" iostandard="LVCMOS33" loc="H15"/>
<pin index="68" name ="spi_ss_i" iostandard="LVCMOS33" loc="T16"/>
</pins>
</part_info>
This diff is collapsed.
This diff is collapsed.
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<part_info part_name="xc7z020clg484-1">
<pins>
<pin index="0" name ="btns_5bits_tri_i_0" iostandard="LVCMOS25" loc="P16"/>
<pin index="1" name ="btns_5bits_tri_i_1" iostandard="LVCMOS25" loc="R16"/>
<pin index="2" name ="btns_5bits_tri_i_2" iostandard="LVCMOS25" loc="N15"/>
<pin index="3" name ="btns_5bits_tri_i_3" iostandard="LVCMOS25" loc="R18"/>
<pin index="4" name ="btns_5bits_tri_i_4" iostandard="LVCMOS25" loc="T18"/>
<pin index="5" name ="leds_8bits_tri_o_0" iostandard="LVCMOS33" loc="T22"/>
<pin index="6" name ="leds_8bits_tri_o_1" iostandard="LVCMOS33" loc="T21"/>
<pin index="7" name ="leds_8bits_tri_o_2" iostandard="LVCMOS33" loc="U22"/>
<pin index="8" name ="leds_8bits_tri_o_3" iostandard="LVCMOS33" loc="U21"/>
<pin index="9" name ="leds_8bits_tri_o_4" iostandard="LVCMOS33" loc="V22"/>
<pin index="10" name ="leds_8bits_tri_o_5" iostandard="LVCMOS33" loc="W22"/>
<pin index="11" name ="leds_8bits_tri_o_6" iostandard="LVCMOS33" loc="U19"/>
<pin index="12" name ="leds_8bits_tri_o_7" iostandard="LVCMOS33" loc="U14"/>
<pin index="13" name ="sws_8bits_tri_i_0" iostandard="LVCMOS25" loc="F22"/>
<pin index="14" name ="sws_8bits_tri_i_1" iostandard="LVCMOS25" loc="G22"/>
<pin index="15" name ="sws_8bits_tri_i_2" iostandard="LVCMOS25" loc="H22"/>
<pin index="16" name ="sws_8bits_tri_i_3" iostandard="LVCMOS25" loc="F21"/>
<pin index="17" name ="sws_8bits_tri_i_4" iostandard="LVCMOS25" loc="H19"/>
<pin index="18" name ="sws_8bits_tri_i_5" iostandard="LVCMOS25" loc="H18"/>
<pin index="19" name ="sws_8bits_tri_i_6" iostandard="LVCMOS25" loc="H17"/>
<pin index="20" name ="sws_8bits_tri_i_7" iostandard="LVCMOS25" loc="M15"/>
<pin index="21" name ="sys_clk" iostandard="LVCMOS33" loc="Y9"/>
<pin index="22" name ="JB1" iostandard="LVCMOS33" loc="W12"/>
<pin index="23" name ="JB2" iostandard="LVCMOS33" loc="W11"/>
<pin index="24" name ="JB3" iostandard="LVCMOS33" loc="V10"/>
<pin index="25" name ="JB4" iostandard="LVCMOS33" loc="W8"/>
<pin index="26" name ="JB7" iostandard="LVCMOS33" loc="V12"/>
<pin index="27" name ="JB8" iostandard="LVCMOS33" loc="W10"/>
<pin index="28" name ="JB9" iostandard="LVCMOS33" loc="V9"/>
<pin index="29" name ="JB10" iostandard="LVCMOS33" loc="V8"/>
<pin index="30" name ="JC1" iostandard="LVCMOS33" loc="AB7"/>
<pin index="31" name ="JC2" iostandard="LVCMOS33" loc="AB6"/>
<pin index="32" name ="JC3" iostandard="LVCMOS33" loc="Y4"/>
<pin index="33" name ="JC4" iostandard="LVCMOS33" loc="AA4"/>
<pin index="34" name ="JC7" iostandard="LVCMOS33" loc="R6"/>
<pin index="35" name ="JC8" iostandard="LVCMOS33" loc="T6"/>
<pin index="36" name ="JC9" iostandard="LVCMOS33" loc="T4"/>
<pin index="37" name ="JC10" iostandard="LVCMOS33" loc="U4"/>
<pin index="38" name ="JA1" iostandard="LVCMOS33" loc="Y11"/>
<pin index="39" name ="JA2" iostandard="LVCMOS33" loc="AA11"/>
<pin index="40" name ="JA3" iostandard="LVCMOS33" loc="Y10"/>
<pin index="41" name ="JA4" iostandard="LVCMOS33" loc="AA9"/>
<pin index="42" name ="JA7" iostandard="LVCMOS33" loc="AB11"/>
<pin index="43" name ="JA8" iostandard="LVCMOS33" loc="AB10"/>
<pin index="44" name ="JA9" iostandard="LVCMOS33" loc="AB9"/>
<pin index="45" name ="JA10" iostandard="LVCMOS33" loc="AA8"/>
<pin index="46" name ="JD1" iostandard="LVCMOS33" loc="V7"/>
<pin index="47" name ="JD2" iostandard="LVCMOS33" loc="W7"/>
<pin index="48" name ="JD3" iostandard="LVCMOS33" loc="V5"/>
<pin index="49" name ="JD4" iostandard="LVCMOS33" loc="V4"/>
<pin index="50" name ="JD7" iostandard="LVCMOS33" loc="W6"/>
<pin index="51" name ="JD8" iostandard="LVCMOS33" loc="W5"/>
<pin index="52" name ="JD9" iostandard="LVCMOS33" loc="U6"/>
<pin index="53" name ="JD10" iostandard="LVCMOS33" loc="U5"/>
<pin index="54" name ="OLED2" iostandard="LVCMOS33" loc="AA12"/>
<pin index="55" name ="OLED4" iostandard="LVCMOS33" loc="AB12"/>
<pin index="56" name ="OLED7" iostandard="LVCMOS33" loc="U10"/>
<pin index="57" name ="OLED8" iostandard="LVCMOS33" loc="U9"/>
<pin index="58" name ="OLED9" iostandard="LVCMOS33" loc="U11"/>
<pin index="59" name ="OLED10" iostandard="LVCMOS33" loc="U12"/>
<pin index="60" name ="usb_uart_rxd" iostandard="LVCMOS18" loc="D11"/>
<pin index="61" name ="usb_uart_txd" iostandard="LVCMOS18" loc="C14"/>
</pins>
</part_info>
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ip_presets schema="1.0">
<ip_preset preset_proc_name="ps7_preset">
<ip vendor="xilinx.com" library="ip" name="processing_system7" version="*">
<user_parameters>
<user_parameter name="CONFIG.preset" value="ZedBoard" />
</user_parameters>
</ip>
</ip_preset>
<ip_preset preset_proc_name="oled_preset">
<ip vendor="digilentinc.com" library="ip" name="pmod_bridge" ip_interface="Pmod_out">
<user_parameters>
<user_parameter name="CONFIG.Top_Row_Interface" value="SPI"/>
<user_parameter name="CONFIG.Bottom_Row_Interface" value="GPIO"/>
</user_parameters>
</ip>
</ip_preset>
<ip_preset preset_proc_name="leds_8bits_preset">
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
<user_parameters>
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="8"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
<user_parameters>
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="8"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
<user_parameters>
<user_parameter name="CONFIG.C_USE_GPO1" value="1"/>
<user_parameter name="CONFIG.C_GPO1_SIZE" value="8"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
<user_parameters>
<user_parameter name="CONFIG.C_USE_GPO2" value="1"/>
<user_parameter name="CONFIG.C_GPO2_SIZE" value="8"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
<user_parameters>
<user_parameter name="CONFIG.C_USE_GPO3" value="1"/>
<user_parameter name="CONFIG.C_GPO3_SIZE" value="8"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
<user_parameters>
<user_parameter name="CONFIG.C_USE_GPO4" value="1"/>
<user_parameter name="CONFIG.C_GPO4_SIZE" value="8"/>
</user_parameters>
</ip>
</ip_preset>
<ip_preset preset_proc_name="sws_8bits_preset">
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
<user_parameters>
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="8"/>
<user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
<user_parameters>
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="8"/>
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
<user_parameters>
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
<user_parameter name="CONFIG.C_GPI1_SIZE" value="8"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
<user_parameters>
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
<user_parameter name="CONFIG.C_GPI2_SIZE" value="8"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
<user_parameters>
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
<user_parameter name="CONFIG.C_GPI3_SIZE" value="8"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
<user_parameters>
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
<user_parameter name="CONFIG.C_GPI4_SIZE" value="8"/>
</ip_preset>
<ip_preset preset_proc_name="btns_5bits_preset">
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
<user_parameters>
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="5"/>
<user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
<user_parameters>
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="5"/>
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
<user_parameters>
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
<user_parameter name="CONFIG.C_GPI1_SIZE" value="5"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
<user_parameters>
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
<user_parameter name="CONFIG.C_GPI2_SIZE" value="5"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
<user_parameters>
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
<user_parameter name="CONFIG.C_GPI3_SIZE" value="5"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
<user_parameters>
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
<user_parameter name="CONFIG.C_GPI4_SIZE" value="5"/>
</user_parameters>
</ip>
</ip_preset>
<ip_preset preset_proc_name="sys_clock_preset">
<ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
<user_parameters>
<user_parameter name="CONFIG.PRIM_IN_FREQ" value="100"/>
<user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
<user_parameters>
<user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
<user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="100"/>
<user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin"/>
</user_parameters>
</ip>
</ip_preset>
<ip_preset preset_proc_name="uart_preset">
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="UART">
<user_parameters>
<user_parameter name="CONFIG.C_USE_UART_RX" value="1"/>
<user_parameter name="CONFIG.C_USE_UART_TX" value="1"/>
</user_parameters>
</ip>
</ip_preset>
<ip_preset preset_proc_name="ps7_preset">
<ip vendor="xilinx.com" library="ip" name="processing_system7" version="*">
<user_parameters>
<user_parameter name="CONFIG.PCW_APU_PERIPHERAL_FREQMHZ" value="650"/>
<user_parameter name="CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ" value="50.000000"/>
<user_parameter name="CONFIG.PCW_ENET0_ENET0_IO" value="MIO 16 .. 27"/>
<user_parameter name="CONFIG.PCW_ENET0_GRP_MDIO_ENABLE" value="1"/>
<user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_ENABLE" value="1"/>
<user_parameter name="CONFIG.PCW_ENET0_RESET_ENABLE" value="0"/>
<user_parameter name="CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ" value="100"/>
<user_parameter name="CONFIG.PCW_GPIO_MIO_GPIO_ENABLE" value="1"/>
<user_parameter name="CONFIG.PCW_MIO_0_PULLUP" value="enabled"/>
<user_parameter name="CONFIG.PCW_MIO_10_PULLUP" value="enabled"/>
<user_parameter name="CONFIG.PCW_MIO_11_PULLUP" value="enabled"/>
<user_parameter name="CONFIG.PCW_MIO_12_PULLUP" value="enabled"/>
<user_parameter name="CONFIG.PCW_MIO_16_IOTYPE" value="HSTL 1.8V"/>
<user_parameter name="CONFIG.PCW_MIO_16_PULLUP" value="disabled"/>
<user_parameter name="CONFIG.PCW_MIO_16_SLEW" value="fast"/>
<user_parameter name="CONFIG.PCW_MIO_17_IOTYPE" value="HSTL 1.8V"/>
<user_parameter name="CONFIG.PCW_MIO_17_PULLUP" value="disabled"/>
<user_parameter name="CONFIG.PCW_MIO_17_SLEW" value="fast"/>
<user_parameter name="CONFIG.PCW_MIO_18_IOTYPE" value="HSTL 1.8V"/>
<user_parameter name="CONFIG.PCW_MIO_18_PULLUP" value="disabled"/>
<user_parameter name="CONFIG.PCW_MIO_18_SLEW" value="fast"/>
<user_parameter name="CONFIG.PCW_MIO_19_IOTYPE" value="HSTL 1.8V"/>
<user_parameter name="CONFIG.PCW_MIO_19_PULLUP" value="disabled"/>
<user_parameter name="CONFIG.PCW_MIO_19_SLEW" value="fast"/>
<user_parameter name="CONFIG.PCW_MIO_1_PULLUP" value="disabled"/>
<user_parameter name="CONFIG.PCW_MIO_1_SLEW" value="fast"/>
<user_parameter name="CONFIG.PCW_MIO_20_IOTYPE" value="HSTL 1.8V"/>
<user_parameter name="CONFIG.PCW_MIO_20_PULLUP" value="disabled"/>
<user_parameter name="CONFIG.PCW_MIO_20_SLEW" value="fast"/>
<user_parameter name="CONFIG.PCW_MIO_21_IOTYPE" value="HSTL 1.8V"/>
<user_parameter name="CONFIG.PCW_MIO_21_PULLUP" value="disabled"/>
<user_parameter name="CONFIG.PCW_MIO_21_SLEW" value="fast"/>
<user_parameter name="CONFIG.PCW_MIO_22_IOTYPE" value="HSTL 1.8V"/>
<user_parameter name="CONFIG.PCW_MIO_22_PULLUP" value="disabled"/>
<user_parameter name="CONFIG.PCW_MIO_22_SLEW" value="fast"/>
<user_parameter name="CONFIG.PCW_MIO_23_IOTYPE" value="HSTL 1.8V"/>
<user_parameter name="CONFIG.PCW_MIO_23_PULLUP" value="disabled"/>
<user_parameter name="CONFIG.PCW_MIO_23_SLEW" value="fast"/>
<user_parameter name="CONFIG.PCW_MIO_24_IOTYPE" value="HSTL 1.8V"/>
<user_parameter name="CONFIG.PCW_MIO_24_PULLUP" value="disabled"/>
<user_parameter name="CONFIG.PCW_MIO_24_SLEW" value="fast"/>
<user_parameter name="CONFIG.PCW_MIO_25_IOTYPE" value="HSTL 1.8V"/>
<user_parameter name="CONFIG.PCW_MIO_25_PULLUP" value="disabled"/>
<user_parameter name="CONFIG.PCW_MIO_25_SLEW" value="fast"/>
<user_parameter name="CONFIG.PCW_MIO_26_IOTYPE" value="HSTL 1.8V"/>
<user_parameter name="CONFIG.PCW_MIO_26_PULLUP" value="disabled"/>
<user_parameter name="CONFIG.PCW_MIO_26_SLEW" value="fast"/>
<user_parameter name="CONFIG.PCW_MIO_27_IOTYPE" value="HSTL 1.8V"/>
<user_parameter name="CONFIG.PCW_MIO_27_PULLUP" value="disabled"/>
<user_parameter name="CONFIG.PCW_MIO_27_SLEW" value="fast"/>
<user_parameter name="CONFIG.PCW_MIO_28_PULLUP" value="disabled"/>
<user_parameter name="CONFIG.PCW_MIO_28_SLEW" value="fast"/>
<user_parameter name="CONFIG.PCW_MIO_29_PULLUP" value="disabled"/>
<user_parameter name="CONFIG.PCW_MIO_29_SLEW" value="fast"/>
<user_parameter name="CONFIG.PCW_MIO_2_SLEW" value="fast"/>
<user_parameter name="CONFIG.PCW_MIO_30_PULLUP" value="disabled"/>
<user_parameter name="CONFIG.PCW_MIO_30_SLEW" value="fast"/>
<user_parameter name="CONFIG.PCW_MIO_31_PULLUP" value="disabled"/>
<user_parameter name="CONFIG.PCW_MIO_31_SLEW" value="fast"/>
<user_parameter name="CONFIG.PCW_MIO_32_PULLUP" value="disabled"/>
<user_parameter name="CONFIG.PCW_MIO_32_SLEW" value="fast"/>
<user_parameter name="CONFIG.PCW_MIO_33_PULLUP" value="disabled"/>
<user_parameter name="CONFIG.PCW_MIO_33_SLEW" value="fast"/>
<user_parameter name="CONFIG.PCW_MIO_34_PULLUP" value="disabled"/>
<user_parameter name="CONFIG.PCW_MIO_34_SLEW" value="fast"/>
<user_parameter name="CONFIG.PCW_MIO_35_PULLUP" value="disabled"/>
<user_parameter name="CONFIG.PCW_MIO_35_SLEW" value="fast"/>
<user_parameter name="CONFIG.PCW_MIO_36_PULLUP" value="disabled"/>
<user_parameter name="CONFIG.PCW_MIO_36_SLEW" value="fast"/>
<user_parameter name="CONFIG.PCW_MIO_37_PULLUP" value="disabled"/>
<user_parameter name="CONFIG.PCW_MIO_37_SLEW" value="fast"/>
<user_parameter name="CONFIG.PCW_MIO_38_PULLUP" value="disabled"/>
<user_parameter name="CONFIG.PCW_MIO_38_SLEW" value="fast"/>
<user_parameter name="CONFIG.PCW_MIO_39_PULLUP" value="disabled"/>
<user_parameter name="CONFIG.PCW_MIO_39_SLEW" value="fast"/>
<user_parameter name="CONFIG.PCW_MIO_3_SLEW" value="fast"/>
<user_parameter name="CONFIG.PCW_MIO_40_PULLUP" value="disabled"/>
<user_parameter name="CONFIG.PCW_MIO_40_SLEW" value="fast"/>
<user_parameter name="CONFIG.PCW_MIO_41_PULLUP" value="disabled"/>
<user_parameter name="CONFIG.PCW_MIO_41_SLEW" value="fast"/>
<user_parameter name="CONFIG.PCW_MIO_42_PULLUP" value="disabled"/>
<user_parameter name="CONFIG.PCW_MIO_42_SLEW" value="fast"/>
<user_parameter name="CONFIG.PCW_MIO_43_PULLUP" value="disabled"/>
<user_parameter name="CONFIG.PCW_MIO_43_SLEW" value="fast"/>
<user_parameter name="CONFIG.PCW_MIO_44_PULLUP" value="disabled"/>
<user_parameter name="CONFIG.PCW_MIO_44_SLEW" value="fast"/>
<user_parameter name="CONFIG.PCW_MIO_45_PULLUP" value="disabled"/>
<user_parameter name="CONFIG.PCW_MIO_45_SLEW" value="fast"/>
<user_parameter name="CONFIG.PCW_MIO_47_PULLUP" value="disabled"/>
<user_parameter name="CONFIG.PCW_MIO_48_PULLUP" value="disabled"/>
<user_parameter name="CONFIG.PCW_MIO_49_PULLUP" value="disabled"/>
<user_parameter name="CONFIG.PCW_MIO_4_SLEW" value="fast"/>
<user_parameter name="CONFIG.PCW_MIO_50_DIRECTION" value="inout"/>
<user_parameter name="CONFIG.PCW_MIO_50_PULLUP" value="disabled"/>
<user_parameter name="CONFIG.PCW_MIO_51_DIRECTION" value="inout"/>
<user_parameter name="CONFIG.PCW_MIO_51_PULLUP" value="disabled"/>
<user_parameter name="CONFIG.PCW_MIO_52_PULLUP" value="disabled"/>
<user_parameter name="CONFIG.PCW_MIO_52_SLEW" value="slow"/>
<user_parameter name="CONFIG.PCW_MIO_53_PULLUP" value="disabled"/>
<user_parameter name="CONFIG.PCW_MIO_53_SLEW" value="slow"/>
<user_parameter name="CONFIG.PCW_MIO_5_SLEW" value="fast"/>
<user_parameter name="CONFIG.PCW_MIO_6_SLEW" value="fast"/>
<user_parameter name="CONFIG.PCW_MIO_8_SLEW" value="fast"/>
<user_parameter name="CONFIG.PCW_MIO_9_PULLUP" value="enabled"/>
<user_parameter name="CONFIG.PCW_PRESET_BANK1_VOLTAGE" value="LVCMOS 1.8V"/>
<user_parameter name="CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE" value="1"/>
<user_parameter name="CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE" value="1"/>
<user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_ENABLE" value="1"/>
<user_parameter name="CONFIG.PCW_SD0_GRP_CD_ENABLE" value="1"/>
<user_parameter name="CONFIG.PCW_SD0_GRP_CD_IO" value="MIO 47"/>
<user_parameter name="CONFIG.PCW_SD0_GRP_WP_ENABLE" value="1"/>
<user_parameter name="CONFIG.PCW_SD0_PERIPHERAL_ENABLE" value="1"/>
<user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ" value="50"/>
<user_parameter name="CONFIG.PCW_TTC0_PERIPHERAL_ENABLE" value="1"/>
<user_parameter name="CONFIG.PCW_UART1_PERIPHERAL_ENABLE" value="1"/>
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0" value="0.176"/>
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1" value="0.159"/>
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2" value="0.162"/>
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3" value="0.187"/>
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0" value="-0.073"/>
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1" value="-0.034"/>
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2" value="-0.03"/>
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3" value="-0.082"/>
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ" value="525"/>
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_PARTNO" value="MT41K128M16 JT-125"/>
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE" value="1"/>
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE" value="1"/>
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL" value="1"/>
<user_parameter name="CONFIG.PCW_USB0_PERIPHERAL_ENABLE" value="1"/>
<user_parameter name="CONFIG.PCW_USB0_RESET_ENABLE" value="1"/>
<user_parameter name="CONFIG.PCW_USB0_RESET_IO" value="MIO 46"/>
</user_parameters>
</ip>
</ip_preset>
</ip_presets>
......@@ -23,7 +23,7 @@
#
# check TAPASCO_HOME env var
if {![info exists ::env(TAPASCO_HOME)]} {
puts "Missing environment variable 'TAPASCO_HOME' - point to TPC root directory."
puts "Missing environment variable 'TAPASCO_HOME' - point to TaPaSCo root directory."
exit 1
}
......@@ -98,9 +98,7 @@ update_compile_order -fileset sources_1
# activate retiming in synthesis
set_property STEPS.SYNTH_DESIGN.ARGS.RETIMING true [get_runs synth_1]
if {[version -short] >= "2016.4"} {
set_property synth_checkpoint_mode None [get_files system.bd]
}
set_property synth_checkpoint_mode None [get_files system.bd]
# generate according to the mode
platform::generate
......
......@@ -107,14 +107,13 @@ namespace eval ::tapasco::ip {
puts "Creating Zynq-7000 series IP core ..."
puts " VLNV: [dict get $stdcomps ps vlnv]"
puts " Preset: $preset"
puts " FCLK0 : $freq_mhz"
set ps [create_bd_cell -type ip -vlnv [dict get $stdcomps ps vlnv] $name]
if {$preset != {} && $preset != ""} {
set_property -dict [list CONFIG.preset $preset] $ps
apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 -config {make_external "FIXED_IO, DDR" apply_board_preset "1" Master "Disable" Slave "Disable" } $ps
} {
apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 -config {make_external "FIXED_IO, DDR" apply_board_preset "0" Master "Disable" Slave "Disable" } $ps
apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 -config {make_external "FIXED_IO, DDR" Master "Disable" Slave "Disable" } $ps
}
return $ps
}
......
......@@ -3,6 +3,7 @@
"Description" : "PyNQ-Z1 Python Productivity for Zynq",
"TclLibrary" : "pynq.tcl",
"Part" : "xc7z020clg400-1",
"BoardPart" : "digilentinc.com:arty-z7-20:part0:1.0",
"TargetUtilization" : 99,
"Benchmark": "pynq.benchmark"
}
set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVCMOS33} [get_ports sys_clk]
create_clock -period 8.000 -name sys_clk_pin -waveform {0.000 4.000} -add [get_ports sys_clk]
#
# Copyright (C) 2017 Jens Korinth, TU Darmstadt
#
# This file is part of Tapasco (TPC).
#
# Tapasco is free software: you can redistribute it and/or modify
# it under the terms of the GNU Lesser General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# Tapasco is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU Lesser General Public License for more details.
#
# You should have received a copy of the GNU Lesser General Public License
# along with Tapasco. If not, see <http://www.gnu.org/licenses/>.
#
# @file clock_constraint.tcl
# @brief Plugin to constraint the sys_clk to the right pin on PyNQ.
# Workaround: PyNQ does not have a Vivado board definition file.
# @author J. Korinth, TU Darmstadt (jk@esa.cs.tu-darmstadt.de)
#
namespace eval clock_constraint {
# Constraints the input pins called 'sys_clk'
proc create_clock_constraint {} {
puts "clock_constraint: setting sys_clk constraint to 125 MHz, 50% duty cycle"
read_xdc -unmanaged "$::env(TAPASCO_HOME)/platform/pynq/plugins/clock.xdc"
}
}
tapasco::register_plugin "platform::clock_constraint::create_clock_constraint" "pre-wrapper"
This diff is collapsed.
......@@ -3,8 +3,8 @@
"Description" : "zedboard Platform",
"TclLibrary" : "zedboard.tcl",
"Part" : "xc7z020clg484-1",
"BoardPart" : "em.avnet.com:zed:part0:1.2",
"BoardPreset" : "zedboard",
"BoardPart" : "digilentinc.com:zedboard:part0:1.0",
"BoardPreset" : "ZedBoard",
"TargetUtilization" : 97,
"Benchmark" : "zedboard.benchmark"
}
......@@ -26,7 +26,6 @@
source -notrace $::env(TAPASCO_HOME)/platform/common/platform.tcl
namespace eval ::platform {
#namespace export create
namespace export max_masters
namespace export get_address_map
......@@ -78,15 +77,16 @@ namespace eval ::platform {
set reset_in [create_bd_pin -dir I -type rst "reset_in"]
set clk_wiz [::tapasco::ip::create_clk_wiz "clk_wiz"]
set_property -dict [list CONFIG.USE_LOCKED {false} CONFIG.USE_RESET {false} CONFIG.NUM_OUT_CLKS [expr "[llength $freqs] / 2"]] $clk_wiz
set clk_mode "sys_diff_clock"
set_property -dict [list CONFIG.USE_LOCKED {false} CONFIG.USE_RESET {false}] $clk_wiz
set clk_mode [lindex [get_board_part_interfaces -filter { NAME =~ sys*clock }] 0]
if {[catch {set_property CONFIG.CLK_IN1_BOARD_INTERFACE {sys_diff_clock} $clk_wiz}]} {
puts " sys_diff_clock is not supported, trying sys_clock instead"
set clk_mode "sys_clock"
if {$clk_mode == ""} {
error "could not find a board interface for the sys clock - check board part?"
}
set_property CONFIG.CLK_IN1_BOARD_INTERFACE $clk_mode $clk_wiz
# check if external port already exists, re-use
if {[catch [get_bd_ports "/$clk_mode"]]} {
if {[get_bd_ports -quiet "/$clk_mode"] != {}} {