Commit f9148c81 authored by Jens Korinth's avatar Jens Korinth
Browse files

Squashed commit of the following:

commit d3245516
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jan 25 10:19:19 2018 +0100

    Closes #149 - Zedboard Synthesis fails for 2017.3 and 2017.4

    * improved sys clock detection by checking available interfaces via
      get_board_part_interfaces, instead of trying sys_diff_clock first
    * also removed second warning when get_bd_pins returns nothing
    * removed old, unused platform code

commit 9a0fb9b0
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jan 25 10:18:03 2018 +0100

    Use Arty-Z7-20 board file from Digilent for PyNQ

    * contains the manually set top.xdc directives
    * identical to Pynq, except for peripheral components

commit f6a25afc
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jan 25 10:16:28 2018 +0100

    Update board definition for zedboard

    * Digilent has newer def of ZedBoard, using that automatically now
    * imported via MYVIVADO / XILINX_PATH env vars

commit a29aa6cc
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jan 25 10:14:39 2018 +0100

    Fix minor bug in PS7 instantiation routine

commit c782eadc
Author: Jens Korinth <jk@esa.cs.tu-darmstadt.de>
Date:   Thu Jan 25 10:13:58 2018 +0100

    Remove 2016.4 specific code from design.master.tcl.template
parent f873c47b
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<board schema_version="2.0" vendor="digilentinc.com" name="arty-z7-20" display_name="Arty Z7-20" url="http://www.digilentinc.com" preset_file="preset.xml" >
<compatible_board_revisions>
<revision id="0">A.0</revision>
</compatible_board_revisions>
<file_version>1.0</file_version>
<description>Arty Z7-20 </description>
<components>
<component name="part0" display_name="Arty Z7-20" type="fpga" part_name="xc7z020clg400-1" pin_map_file="part0_pins.xml" vendor="xilinx.com" spec_url="http://www.digilentinc.com">
<interfaces>
<interface mode="master" name="btns_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="btns_4bits" preset_proc="push_buttons_4bits_preset">
<port_maps>
<port_map logical_port="TRI_I" physical_port="btns_4bits_tri_i" dir="in" left="3" right="0">
<pin_maps>
<pin_map port_index="0" component_pin="btns_4bits_tri_i_0"/>
<pin_map port_index="1" component_pin="btns_4bits_tri_i_1"/>
<pin_map port_index="2" component_pin="btns_4bits_tri_i_2"/>
<pin_map port_index="3" component_pin="btns_4bits_tri_i_3"/>
</pin_maps>
</port_map>
</port_maps>
</interface>
<interface mode="master" name="leds_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="leds_4bits" preset_proc="led_4bits_preset">
<port_maps>
<port_map logical_port="TRI_O" physical_port="leds_4bits_tri_o" dir="out" left="3" right="0">
<pin_maps>
<pin_map port_index="0" component_pin="leds_4bits_tri_o_0"/>
<pin_map port_index="1" component_pin="leds_4bits_tri_o_1"/>
<pin_map port_index="2" component_pin="leds_4bits_tri_o_2"/>
<pin_map port_index="3" component_pin="leds_4bits_tri_o_3"/>
</pin_maps>
</port_map>
<port_map logical_port="TRI_I" physical_port="leds_4bits_tri_o" dir="in" left="3" right="0">
<pin_maps>
<pin_map port_index="0" component_pin="leds_4bits_tri_o_0"/>
<pin_map port_index="1" component_pin="leds_4bits_tri_o_1"/>
<pin_map port_index="2" component_pin="leds_4bits_tri_o_2"/>
<pin_map port_index="3" component_pin="leds_4bits_tri_o_3"/>
</pin_maps>
</port_map>
<port_map logical_port="TRI_T" physical_port="leds_4bits_tri_o" dir="out" left="3" right="0">
<pin_maps>
<pin_map port_index="0" component_pin="leds_4bits_tri_o_0"/>
<pin_map port_index="1" component_pin="leds_4bits_tri_o_1"/>
<pin_map port_index="2" component_pin="leds_4bits_tri_o_2"/>
<pin_map port_index="3" component_pin="leds_4bits_tri_o_3"/>
</pin_maps>
</port_map>
</port_maps>
</interface>
<interface mode="master" name="ps7_fixedio" type="xilinx.com:display_processing_system7:fixedio_rtl:1.0" of_component="ps7_fixedio" preset_proc="ps7_preset">
</interface>
<interface mode="master" name="sws_2bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="sws_2bits" preset_proc="dip_switches_2bits_preset">
<port_maps>
<port_map logical_port="TRI_I" physical_port="sws_2bits_tri_i" dir="in" left="1" right="0">
<pin_maps>
<pin_map port_index="0" component_pin="sws_2bits_tri_i_0"/>
<pin_map port_index="1" component_pin="sws_2bits_tri_i_1"/>
</pin_maps>
</port_map>
</port_maps>
</interface>
<interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_clock_preset">
<port_maps>
<port_map logical_port="CLK" physical_port="sys_clk" dir="in">
<pin_maps>
<pin_map port_index="0" component_pin="sys_clk"/>
</pin_maps>
</port_map>
</port_maps>
<parameters>
<parameter name="frequency" value="125000000" />
</parameters>
</interface>
<interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
<port_maps>
<port_map logical_port="PIN1_I" physical_port="JA1" dir="in">
<pin_maps>
<pin_map port_index="0" component_pin="JA1"/>
</pin_maps>
</port_map>
<port_map logical_port="PIN1_O" physical_port="JA1" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="JA1"/>
</pin_maps>
</port_map>
<port_map logical_port="PIN1_T" physical_port="JA1" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="JA1"/>
</pin_maps>
</port_map>
<port_map logical_port="PIN2_I" physical_port="JA2" dir="in">
<pin_maps>
<pin_map port_index="0" component_pin="JA2"/>
</pin_maps>
</port_map>
<port_map logical_port="PIN2_O" physical_port="JA2" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="JA2"/>
</pin_maps>
</port_map>
<port_map logical_port="PIN2_T" physical_port="JA2" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="JA2"/>
</pin_maps>
</port_map>
<port_map logical_port="PIN3_I" physical_port="JA3" dir="in">
<pin_maps>
<pin_map port_index="0" component_pin="JA3"/>
</pin_maps>
</port_map>
<port_map logical_port="PIN3_O" physical_port="JA3" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="JA3"/>
</pin_maps>
</port_map>
<port_map logical_port="PIN3_T" physical_port="JA3" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="JA3"/>
</pin_maps>
</port_map>
<port_map logical_port="PIN4_I" physical_port="JA4" dir="in">
<pin_maps>
<pin_map port_index="0" component_pin="JA4"/>
</pin_maps>
</port_map>
<port_map logical_port="PIN4_O" physical_port="JA4" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="JA4"/>
</pin_maps>
</port_map>
<port_map logical_port="PIN4_T" physical_port="JA4" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="JA4"/>
</pin_maps>
</port_map>
<port_map logical_port="PIN7_I" physical_port="JA7" dir="in">
<pin_maps>
<pin_map port_index="0" component_pin="JA7"/>
</pin_maps>
</port_map>
<port_map logical_port="PIN7_O" physical_port="JA7" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="JA7"/>
</pin_maps>
</port_map>
<port_map logical_port="PIN7_T" physical_port="JA7" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="JA7"/>
</pin_maps>
</port_map>
<port_map logical_port="PIN8_I" physical_port="JA8" dir="in">
<pin_maps>
<pin_map port_index="0" component_pin="JA8"/>
</pin_maps>
</port_map>
<port_map logical_port="PIN8_O" physical_port="JA8" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="JA8"/>
</pin_maps>
</port_map>
<port_map logical_port="PIN8_T" physical_port="JA8" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="JA8"/>
</pin_maps>
</port_map>
<port_map logical_port="PIN9_I" physical_port="JA9" dir="in">
<pin_maps>
<pin_map port_index="0" component_pin="JA9"/>
</pin_maps>
</port_map>
<port_map logical_port="PIN9_O" physical_port="JA9" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="JA9"/>
</pin_maps>
</port_map>
<port_map logical_port="PIN9_T" physical_port="JA9" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="JA9"/>
</pin_maps>
</port_map>
<port_map logical_port="PIN10_I" physical_port="JA10" dir="in">
<pin_maps>
<pin_map port_index="0" component_pin="JA10"/>
</pin_maps>
</port_map>
<port_map logical_port="PIN10_O" physical_port="JA10" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="JA10"/>
</pin_maps>
</port_map>
<port_map logical_port="PIN10_T" physical_port="JA10" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="JA10"/>
</pin_maps>
</port_map>
</port_maps>
</interface>
<interface mode="master" name="jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jb">
<port_maps>
<port_map logical_port="PIN1_I" physical_port="JB1" dir="in">
<pin_maps>
<pin_map port_index="0" component_pin="JB1"/>
</pin_maps>
</port_map>
<port_map logical_port="PIN1_O" physical_port="JB1" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="JB1"/>
</pin_maps>
</port_map>
<port_map logical_port="PIN1_T" physical_port="JB1" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="JB1"/>
</pin_maps>
</port_map>
<port_map logical_port="PIN2_I" physical_port="JB2" dir="in">
<pin_maps>
<pin_map port_index="0" component_pin="JB2"/>
</pin_maps>
</port_map>
<port_map logical_port="PIN2_O" physical_port="JB2" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="JB2"/>
</pin_maps>
</port_map>
<port_map logical_port="PIN2_T" physical_port="JB2" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="JB2"/>
</pin_maps>
</port_map>
<port_map logical_port="PIN3_I" physical_port="JB3" dir="in">
<pin_maps>
<pin_map port_index="0" component_pin="JB3"/>
</pin_maps>
</port_map>
<port_map logical_port="PIN3_O" physical_port="JB3" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="JB3"/>
</pin_maps>
</port_map>
<port_map logical_port="PIN3_T" physical_port="JB3" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="JB3"/>
</pin_maps>
</port_map>
<port_map logical_port="PIN4_I" physical_port="JB4" dir="in">
<pin_maps>
<pin_map port_index="0" component_pin="JB4"/>
</pin_maps>
</port_map>
<port_map logical_port="PIN4_O" physical_port="JB4" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="JB4"/>
</pin_maps>
</port_map>
<port_map logical_port="PIN4_T" physical_port="JB4" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="JB4"/>
</pin_maps>
</port_map>
<port_map logical_port="PIN7_I" physical_port="JB7" dir="in">
<pin_maps>
<pin_map port_index="0" component_pin="JB7"/>
</pin_maps>
</port_map>
<port_map logical_port="PIN7_O" physical_port="JB7" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="JB7"/>
</pin_maps>
</port_map>
<port_map logical_port="PIN7_T" physical_port="JB7" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="JB7"/>
</pin_maps>
</port_map>
<port_map logical_port="PIN8_I" physical_port="JB8" dir="in">
<pin_maps>
<pin_map port_index="0" component_pin="JB8"/>
</pin_maps>
</port_map>
<port_map logical_port="PIN8_O" physical_port="JB8" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="JB8"/>
</pin_maps>
</port_map>
<port_map logical_port="PIN8_T" physical_port="JB8" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="JB8"/>
</pin_maps>
</port_map>
<port_map logical_port="PIN9_I" physical_port="JB9" dir="in">
<pin_maps>
<pin_map port_index="0" component_pin="JB9"/>
</pin_maps>
</port_map>
<port_map logical_port="PIN9_O" physical_port="JB9" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="JB9"/>
</pin_maps>
</port_map>
<port_map logical_port="PIN9_T" physical_port="JB9" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="JB9"/>
</pin_maps>
</port_map>
<port_map logical_port="PIN10_I" physical_port="JB10" dir="in">
<pin_maps>
<pin_map port_index="0" component_pin="JB10"/>
</pin_maps>
</port_map>
<port_map logical_port="PIN10_O" physical_port="JB10" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="JB10"/>
</pin_maps>
</port_map>
<port_map logical_port="PIN10_T" physical_port="JB10" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="JB10"/>
</pin_maps>
</port_map>
</port_maps>
</interface>
<interface mode="master" name="i2c" type="xilinx.com:interface:iic_rtl:1.0" of_component="i2c">
<description>Shield I2C</description>
<preferred_ips>
<preferred_ip vendor="xilinx.com" library="ip" name="axi_iic" order="0"/>
</preferred_ips>
<port_maps>
<port_map logical_port="SDA_I" physical_port="i2c_sda_i" dir="in">
<pin_maps>
<pin_map port_index="0" component_pin="i2c_sda_i"/>
</pin_maps>
</port_map>
<port_map logical_port="SDA_O" physical_port="i2c_sda_o" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="i2c_sda_i"/>
</pin_maps>
</port_map>
<port_map logical_port="SDA_T" physical_port="i2c_sda_t" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="i2c_sda_i"/>
</pin_maps>
</port_map>
<port_map logical_port="SCL_I" physical_port="i2c_scl_i" dir="in">
<pin_maps>
<pin_map port_index="0" component_pin="i2c_scl_i"/>
</pin_maps>
</port_map>
<port_map logical_port="SCL_O" physical_port="i2c_scl_o" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="i2c_scl_i"/>
</pin_maps>
</port_map>
<port_map logical_port="SCL_T" physical_port="i2c_scl_t" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="i2c_scl_i"/>
</pin_maps>
</port_map>
</port_maps>
</interface>
<interface mode="master" name="rgb_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgb_led" preset_proc="output_6bits_preset">
<description>2 RGB LEDs</description>
<preferred_ips>
<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
</preferred_ips>
<port_maps>
<port_map logical_port="TRI_O" physical_port="rgb_led_tri_o" dir="out" left="5" right="0">
<pin_maps>
<pin_map port_index="0" component_pin="rgb_led_tri_o_0"/>
<pin_map port_index="1" component_pin="rgb_led_tri_o_1"/>
<pin_map port_index="2" component_pin="rgb_led_tri_o_2"/>
<pin_map port_index="3" component_pin="rgb_led_tri_o_3"/>
<pin_map port_index="4" component_pin="rgb_led_tri_o_4"/>
<pin_map port_index="5" component_pin="rgb_led_tri_o_5"/>
</pin_maps>
</port_map>
<port_map logical_port="TRI_I" physical_port="rgb_led_tri_o" dir="in" left="5" right="0">
<pin_maps>
<pin_map port_index="0" component_pin="rgb_led_tri_o_0"/>
<pin_map port_index="1" component_pin="rgb_led_tri_o_1"/>
<pin_map port_index="2" component_pin="rgb_led_tri_o_2"/>
<pin_map port_index="3" component_pin="rgb_led_tri_o_3"/>
<pin_map port_index="4" component_pin="rgb_led_tri_o_4"/>
<pin_map port_index="5" component_pin="rgb_led_tri_o_5"/>
</pin_maps>
</port_map>
<port_map logical_port="TRI_T" physical_port="rgb_led_tri_o" dir="out" left="5" right="0">
<pin_maps>
<pin_map port_index="0" component_pin="rgb_led_tri_o_0"/>
<pin_map port_index="1" component_pin="rgb_led_tri_o_1"/>
<pin_map port_index="2" component_pin="rgb_led_tri_o_2"/>
<pin_map port_index="3" component_pin="rgb_led_tri_o_3"/>
<pin_map port_index="4" component_pin="rgb_led_tri_o_4"/>
<pin_map port_index="5" component_pin="rgb_led_tri_o_5"/>
</pin_maps>
</port_map>
</port_maps>
</interface>
<interface mode="master" name="shield_dp0_dp13" type="xilinx.com:interface:gpio_rtl:1.0" of_component="shield_dp0_dp13" preset_proc="shield_dp0_dp13_preset">
<preferred_ips>
<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
</preferred_ips>
<port_maps>
<port_map logical_port="TRI_I" physical_port="shield_dp0_dp13_tri_i" dir="in" left="13" right="0">
<pin_maps>
<pin_map port_index="0" component_pin="shield_dp0_dp13_tri_i_0"/>
<pin_map port_index="1" component_pin="shield_dp0_dp13_tri_i_1"/>
<pin_map port_index="2" component_pin="shield_dp0_dp13_tri_i_2"/>
<pin_map port_index="3" component_pin="shield_dp0_dp13_tri_i_3"/>
<pin_map port_index="4" component_pin="shield_dp0_dp13_tri_i_4"/>
<pin_map port_index="5" component_pin="shield_dp0_dp13_tri_i_5"/>
<pin_map port_index="6" component_pin="shield_dp0_dp13_tri_i_6"/>
<pin_map port_index="7" component_pin="shield_dp0_dp13_tri_i_7"/>
<pin_map port_index="8" component_pin="shield_dp0_dp13_tri_i_8"/>
<pin_map port_index="9" component_pin="shield_dp0_dp13_tri_i_9"/>
<pin_map port_index="10" component_pin="shield_dp0_dp13_tri_i_10"/>
<pin_map port_index="11" component_pin="shield_dp0_dp13_tri_i_11"/>
<pin_map port_index="12" component_pin="shield_dp0_dp13_tri_i_12"/>
<pin_map port_index="13" component_pin="shield_dp0_dp13_tri_i_13"/>
</pin_maps>
</port_map>
<port_map logical_port="TRI_O" physical_port="shield_dp0_dp13_tri_o" dir="out" left="13" right="0">
<pin_maps>
<pin_map port_index="0" component_pin="shield_dp0_dp13_tri_i_0"/>
<pin_map port_index="1" component_pin="shield_dp0_dp13_tri_i_1"/>
<pin_map port_index="2" component_pin="shield_dp0_dp13_tri_i_2"/>
<pin_map port_index="3" component_pin="shield_dp0_dp13_tri_i_3"/>
<pin_map port_index="4" component_pin="shield_dp0_dp13_tri_i_4"/>
<pin_map port_index="5" component_pin="shield_dp0_dp13_tri_i_5"/>
<pin_map port_index="6" component_pin="shield_dp0_dp13_tri_i_6"/>
<pin_map port_index="7" component_pin="shield_dp0_dp13_tri_i_7"/>
<pin_map port_index="8" component_pin="shield_dp0_dp13_tri_i_8"/>
<pin_map port_index="9" component_pin="shield_dp0_dp13_tri_i_9"/>
<pin_map port_index="10" component_pin="shield_dp0_dp13_tri_i_10"/>
<pin_map port_index="11" component_pin="shield_dp0_dp13_tri_i_11"/>
<pin_map port_index="12" component_pin="shield_dp0_dp13_tri_i_12"/>
<pin_map port_index="13" component_pin="shield_dp0_dp13_tri_i_13"/>
</pin_maps>
</port_map>
<port_map logical_port="TRI_T" physical_port="shield_dp0_dp13_tri_t" dir="out" left="13" right="0">
<pin_maps>
<pin_map port_index="0" component_pin="shield_dp0_dp13_tri_i_0"/>
<pin_map port_index="1" component_pin="shield_dp0_dp13_tri_i_1"/>
<pin_map port_index="2" component_pin="shield_dp0_dp13_tri_i_2"/>
<pin_map port_index="3" component_pin="shield_dp0_dp13_tri_i_3"/>
<pin_map port_index="4" component_pin="shield_dp0_dp13_tri_i_4"/>
<pin_map port_index="5" component_pin="shield_dp0_dp13_tri_i_5"/>
<pin_map port_index="6" component_pin="shield_dp0_dp13_tri_i_6"/>
<pin_map port_index="7" component_pin="shield_dp0_dp13_tri_i_7"/>
<pin_map port_index="8" component_pin="shield_dp0_dp13_tri_i_8"/>
<pin_map port_index="9" component_pin="shield_dp0_dp13_tri_i_9"/>
<pin_map port_index="10" component_pin="shield_dp0_dp13_tri_i_10"/>
<pin_map port_index="11" component_pin="shield_dp0_dp13_tri_i_11"/>
<pin_map port_index="12" component_pin="shield_dp0_dp13_tri_i_12"/>
<pin_map port_index="13" component_pin="shield_dp0_dp13_tri_i_13"/>
</pin_maps>
</port_map>
</port_maps>
</interface>
<interface mode="master" name="shield_dp26_dp41" type="xilinx.com:interface:gpio_rtl:1.0" of_component="shield_dp26_dp41" preset_proc="shield_dp26_dp41_preset">
<preferred_ips>
<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
</preferred_ips>
<port_maps>
<port_map logical_port="TRI_I" physical_port="shield_dp26_dp41_tri_i" dir="in" left="15" right="0">
<pin_maps>
<pin_map port_index="0" component_pin="shield_dp26_dp41_tri_i_0"/>
<pin_map port_index="1" component_pin="shield_dp26_dp41_tri_i_1"/>
<pin_map port_index="2" component_pin="shield_dp26_dp41_tri_i_2"/>
<pin_map port_index="3" component_pin="shield_dp26_dp41_tri_i_3"/>
<pin_map port_index="4" component_pin="shield_dp26_dp41_tri_i_4"/>
<pin_map port_index="5" component_pin="shield_dp26_dp41_tri_i_5"/>
<pin_map port_index="6" component_pin="shield_dp26_dp41_tri_i_6"/>
<pin_map port_index="7" component_pin="shield_dp26_dp41_tri_i_7"/>
<pin_map port_index="8" component_pin="shield_dp26_dp41_tri_i_8"/>
<pin_map port_index="9" component_pin="shield_dp26_dp41_tri_i_9"/>
<pin_map port_index="10" component_pin="shield_dp26_dp41_tri_i_10"/>
<pin_map port_index="11" component_pin="shield_dp26_dp41_tri_i_11"/>
<pin_map port_index="12" component_pin="shield_dp26_dp41_tri_i_12"/>
<pin_map port_index="13" component_pin="shield_dp26_dp41_tri_i_13"/>
<pin_map port_index="14" component_pin="shield_dp26_dp41_tri_i_14"/>
<pin_map port_index="15" component_pin="shield_dp26_dp41_tri_i_15"/>
</pin_maps>
</port_map>
<port_map logical_port="TRI_O" physical_port="shield_dp26_dp41_tri_o" dir="out" left="15" right="0">
<pin_maps>
<pin_map port_index="0" component_pin="shield_dp26_dp41_tri_i_0"/>
<pin_map port_index="1" component_pin="shield_dp26_dp41_tri_i_1"/>
<pin_map port_index="2" component_pin="shield_dp26_dp41_tri_i_2"/>
<pin_map port_index="3" component_pin="shield_dp26_dp41_tri_i_3"/>
<pin_map port_index="4" component_pin="shield_dp26_dp41_tri_i_4"/>
<pin_map port_index="5" component_pin="shield_dp26_dp41_tri_i_5"/>
<pin_map port_index="6" component_pin="shield_dp26_dp41_tri_i_6"/>
<pin_map port_index="7" component_pin="shield_dp26_dp41_tri_i_7"/>
<pin_map port_index="8" component_pin="shield_dp26_dp41_tri_i_8"/>
<pin_map port_index="9" component_pin="shield_dp26_dp41_tri_i_9"/>
<pin_map port_index="10" component_pin="shield_dp26_dp41_tri_i_10"/>
<pin_map port_index="11" component_pin="shield_dp26_dp41_tri_i_11"/>
<pin_map port_index="12" component_pin="shield_dp26_dp41_tri_i_12"/>
<pin_map port_index="13" component_pin="shield_dp26_dp41_tri_i_13"/>
<pin_map port_index="14" component_pin="shield_dp26_dp41_tri_i_14"/>
<pin_map port_index="15" component_pin="shield_dp26_dp41_tri_i_15"/>
</pin_maps>
</port_map>
<port_map logical_port="TRI_T" physical_port="shield_dp26_dp41_tri_t" dir="out" left="15" right="0">
<pin_maps>
<pin_map port_index="0" component_pin="shield_dp26_dp41_tri_i_0"/>
<pin_map port_index="1" component_pin="shield_dp26_dp41_tri_i_1"/>
<pin_map port_index="2" component_pin="shield_dp26_dp41_tri_i_2"/>
<pin_map port_index="3" component_pin="shield_dp26_dp41_tri_i_3"/>
<pin_map port_index="4" component_pin="shield_dp26_dp41_tri_i_4"/>
<pin_map port_index="5" component_pin="shield_dp26_dp41_tri_i_5"/>
<pin_map port_index="6" component_pin="shield_dp26_dp41_tri_i_6"/>
<pin_map port_index="7" component_pin="shield_dp26_dp41_tri_i_7"/>
<pin_map port_index="8" component_pin="shield_dp26_dp41_tri_i_8"/>
<pin_map port_index="9" component_pin="shield_dp26_dp41_tri_i_9"/>
<pin_map port_index="10" component_pin="shield_dp26_dp41_tri_i_10"/>
<pin_map port_index="11" component_pin="shield_dp26_dp41_tri_i_11"/>
<pin_map port_index="12" component_pin="shield_dp26_dp41_tri_i_12"/>
<pin_map port_index="13" component_pin="shield_dp26_dp41_tri_i_13"/>
<pin_map port_index="14" component_pin="shield_dp26_dp41_tri_i_14"/>
<pin_map port_index="15" component_pin="shield_dp26_dp41_tri_i_15"/>
</pin_maps>
</port_map>
</port_maps>
</interface>
<interface mode="master" name="spi" type="xilinx.com:interface:spi_rtl:1.0" of_component="spi" preset_proc="spi_preset">
<preferred_ips>
<preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
</preferred_ips>
<port_maps>
<port_map logical_port="IO0_I" physical_port="spi_miso_i" dir="in">
<pin_maps>
<pin_map port_index="0" component_pin="spi_miso_i"/>
</pin_maps>
</port_map>
<port_map logical_port="IO0_O" physical_port="spi_miso_o" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="spi_miso_i"/>
</pin_maps>
</port_map>
<port_map logical_port="IO0_T" physical_port="spi_miso_t" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="spi_miso_i"/>
</pin_maps>
</port_map>
<port_map logical_port="IO1_I" physical_port="spi_mosi_i" dir="in">
<pin_maps>
<pin_map port_index="0" component_pin="spi_mosi_i"/>
</pin_maps>
</port_map>
<port_map logical_port="IO1_O" physical_port="spi_mosi_o" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="spi_mosi_i"/>
</pin_maps>
</port_map>
<port_map logical_port="IO1_T" physical_port="spi_mosi_t" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="spi_mosi_i"/>
</pin_maps>
</port_map>
<port_map logical_port="SCK_I" physical_port="spi_sclk_i" dir="in">
<pin_maps>
<pin_map port_index="0" component_pin="spi_sclk_i"/>
</pin_maps>
</port_map>
<port_map logical_port="SCK_O" physical_port="spi_sclk_o" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="spi_sclk_i"/>
</pin_maps>
</port_map>
<port_map logical_port="SCK_T" physical_port="spi_sclk_t" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="spi_sclk_i"/>
</pin_maps>
</port_map>
<port_map logical_port="SS_I" physical_port="spi_ss_i" dir="in">
<pin_maps>
<pin_map port_index="0" component_pin="spi_ss_i"/>
</pin_maps>
</port_map>
<port_map logical_port="SS_O" physical_port="spi_ss_o" dir="out">