* AXI mandates that all ready signals be low during reset
* unfortunately, not only is this not the case in Queues, but they
  actively start working while reset is high (insane)
* fixed by manually pulling the signals low on reset
* tested with Xilinx AXI Verification IP, all's well

* entirely based on Queues now, fixed firing logic
* still with workaround for problem in Queue with optional fields
* simplified ProgrammableMaster
* changed Registers write method to return Response instead of Boolean
* switched completely to Spec testing: register files are generated
  ad-hoc, corresponding master program and testing steps are
  automatically generated

* replaced FSM approach with Queues; each channel has its own Queue, and
  all is handled using the handshakes
* simple, because 1-cycle reads and writes can be guaranteed

* new scheme: chisel.axi is the main package
* chisel.axi.Axi4 contains the full axi defs
* chisel.axi.Axi4Lite contains the lite defs
* chisel.axi.axi4 contains full Axi4 impls
* chisel.axi.axi4lite contains lite impls
* same applies for the generators, matching structure

*  split into subpackages axi4 and axi4lite
*  moved each module into its subpackage
*  shortened names by removing Axi-prefixes wherever possible
*  moved Configs and IOs into corresponding companion object
*  replaced some printlns/printfs with Logging facilities